互连封装结构电特性分析中的改进PEEC三维建模

本文提出了一种改进的PEEC模型,为便于在大规模互连封装结构分析中利用规模缩减技术,它以描述系统的状态方程代替了具体的等效电路.为此它以矢量磁位的积分表达式和洛仑兹规范代替了矢量磁位和标量电位的积分表达式,对积分方程进行展开.这样做可以避免复杂介质结构中的电容矩阵提取,大大节省了计算时间.这一模型可方便地嵌入更大的系统进行分层次的综合分析和利用PVL等规模缩减技术.数值计算的结果与其他文献吻合较好,表明该方法有较高的可靠性.     

Generalized Partial-Element Equivalent-Circuit Analysis for Planar Circuits With Slotted Ground

A generalized partial-element equivalent-circuit (PEEC) method is proposed for modeling a planar circuit with a thin narrow slot on the ground. The approach is based on the coupled mixed potential integral equations for a problem with mixed electric and magnetic currents. The coupled integral equations are converted into a lumped-element circuit network using Kirchhoff's voltage law and Kirchhoff's current law of the circuit theory. The full-wave Green's functions for a grounded dielectric substrate problem are used. The interactions between electric current on a microstrip line and magnetic current on a slot are taken into account by introducing two kinds of controlled sources. This generalized PEEC model will be very useful in signal-integrity analysis for multilayered circuits. To validate the generalized model, three numerical examples consisting of microstrip lines and slots on the ground are presented. The results obtained by the proposed generalized PEEC model are compared with those obtained by commercial electromagnetic simulation software and published experimental results. Good agreement is obtained.      

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.     

Frequency response characteristics of reference plane effectiveinductance and resistance [IC packaging]

A method which uses the partial element equivalent circuit (PEEC) method and electrical network theory to solve for the effective impedance matrix of reference planes is presented. The convergence and accuracy of the method are checked. The frequency responses of the effective inductance (L_eff(f)) and resistance (R_eff(f)) of reference plane are discussed. The effects of current redistribution and the skin effect on L_eff(f) and R _eff(f) are discussed. The effect of number of sinks and sources is examined     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics     

Fast multipole method for time domain PEEC analysis

High-speed electronic circuits are becoming more and more important in modern communication systems, thus leading to an increasing interest in printed circuit boards, interconnect, and packaging. Nowadays, full-wave numerical methods are widely used in order to investigate both signal integrity and electromagnetic compatibility issues arising in PCBs design. When broadband information is desired and transient effects dominate, it is more efficient using time domain numerical techniques, which may scale better than corresponding frequency-domain methods. This paper presents the derivation of the time domain partial element equivalent circuit (PEEC) method enhanced by the three-dimensional (3D) fast multipole method (FMM). It is shown that combining the full-wave time domain PEEC method with the FMM allows performing the analysis of electrically large electronic systems, which reduces both memory and CPU-time requirements. Several examples are presented confirming the capability of the proposed approach to provide a significant reduction of the computational complexity associated with the transient analysis of large systems.     

Accuracy and stability improvements of integral equation modelsusing the partial element equivalent circuit (PEEC) approach

The partial element equivalent circuit (PEEC) technique is a formulation which transforms an electric field integral equation (EFIE) into a full-wave equivalent circuit solution. In this paper, improvements are made to the PEEC model through the development of a refined method of computing both the partial inductances as well as the coefficients of potential. The method does not increase the number of unknowns. In addition, damping is added to the PEEC model in order to further reduce nonphysical resonances which may occur above the useful frequency range, The observations and solutions presented in this paper are especially important for time domain solvers. The effectiveness of the method is illustrated with several examples     

Iterative reweighted least-squares design of FIR filters

Develops a new iterative reweighted least squares algorithm for the design of optimal L_p approximation FIR filters. The algorithm combines a variable p technique with a Newton's method to give excellent robust initial convergence and quadratic final convergence. Details of the convergence properties when applied to the L_p optimization problem are given. The primary purpose of L_p approximation for filter design is to allow design with different error criteria in pass and stopband and to design constrained L₂ approximation filters. The new method can also be applied to the complex Chebyshev approximation problem and to the design of 2D FIR filters     

A three-terminal band-trap-band tunneling model for drainengineering and substrate bias effect on GIDL in MOSFET

A new three-terminal partial band-trap-band tunneling (BTB) model is proposed to predict the drain engineering effect and substrate bias effect on gate-induced-drain-leakage (GIDL) characteristics for virgin devices free from electric stress. The lateral field ϵ_L and the ratio of lateral field w.r.t. total field ϵ(ϵ_L /ϵ) are two key factors responsible for the tunneling barrier lowering and the enhancement of GIDL. The principle to suppress GIDL are two-fold: the first one is to eliminate process induced intrinsic interface states and the second one is to minimize ϵ_L and ϵ_L/ϵ by using drain engineering or changing bias conditions such as applying forward substrate biases     

高速MCM布线网互连和封装效应的计算机仿真

本文针对高速MCM布线网中由互连和封装引起的寄生效应提出了进行计算机仿真的方法.此方法以兰召斯Pade逼近算法(PVL)为基础,综合了部分元等效电路的三维模型,微分求积法的互连线宏模型,求解包含通孔、多导体互连线和集总元件组成的复杂线网对高速脉冲信号的响应.为分析高速MCM设计中的电特性问题提供了高效的工具.     

FDTD analysis of high frequency electronic interconnection effects

A full-wave analysis of coupled high-frequency interconnect discontinuities is presented using the finite-difference time-domain (FDTD) method. The electromagnetic effects of two via holes on microstrip lines in close proximity to one another are examined and equivalent circuits are presented. The effects of two adjacent lines with bond wires, used, for example, to connect a die to the leadframe of an integrated circuit (IC) package are also analyzed. Frequency domain results are presented by using the discrete Fourier transform of the time-domain results. Guidelines regarding the effective use of the FDTD code including the use a priori calculated electric field distribution in the excitation plane, and the use of a weighted ϵ_r,eff to minimize reflections at the absorbing boundaries are described. The obtained FDTD results and the developed equivalent circuit models show the importance of radiation effects at frequencies beyond 20-30 GHz, the possibilities of reducing the inductive effect of bond wires by using two parallel bond wires instead of one, and the importance of including mutual inductance elements in the equivalent circuit model to account for the crosstalk between parallel vias across a ground plane     

Fast multipole and multifunction PEEC methods

A key use of the partial element equivalent circuit (PEEC) method is the solution of combined electromagnetic and circuit problems as they occur in many situations such as today's integrated circuit (VLSI) systems and as components in mobile devices. The method, which has been applied to a multitude of electrical interconnect and package problems, is very flexible since it is easy to add new features to the approach. However, faster solutions are of interest since the problems to be solved are continuously increasing size. A class of fast methods is evolving based on the faster evaluation of the matrix elements and the use of iterative or other matrix solvers of the resultant system for the frequency domain. Fast circuit matrix solvers are easier to obtain in the time domain than the frequency domain since the delay or retardation can be utilized to sparsify the circuit matrix. In this paper, we concentrate on techniques for the fast evaluation of the PEEC circuit element for both the frequency and time domain where possible since both are important for the solution of specific problems.     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.     

Analysis of dispersion and series gap discontinuity in shieldedsuspended striplines with substrate mounting grooves

Dispersion and series gap discontinuity of shielded suspended striplines (SSLs) on Duroid substrate (ϵ_r=2.22) are analyzed using the finite-difference time-domain method (FD-TD). Numerical accuracy of better than 0.15% is achieved when the FD-TD is used to calculate the effective dielectric constant (ϵ_reff ) of an air-filled rectangular coaxial transmission line. Data obtained for the frequency-dependent ϵ_reff of uniform SSLs and both scattering and equivalent circuit parameters of various series gap discontinuities are presented. In general, the presence of sidewall mounting grooves causes a nearly frequency-independent small reduction in ϵ_reff. On the other hand, proximity effects of the housing are found to be more important. For the gap discontinuity, coupling across the gap is stronger for wider strips and/or narrower gap width. Irregular transmission behavior is also found when the strip is wide enough to interact strongly with the sidewalls     

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

面向当今封装的挠性印制电路板

挠性电路的特征适合于元件之间要求高密度互连的应用,其安装和连接的挠性特征,高密度电路的精确能力,耐热性能,电路终端选择的多样性以及材料和空间的有效使用等使挠性电路在当前和未来的封装应用中具有广阔的应用前景。     

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.