A MOS LSI capacitive keyboard interface chip

A single chip silicon gate LSI device is described which interfaces a microprocessor to a capacitive keyboard. The LSI circuit replaces a large number of MSI devices and substitutes a unique digital key detection scheme for the more traditional differential amplifiers. On chip are an internal oscillator, a clock generator, key matrix scanning and detection circuits, a digital filter, input sensing circuits with hysteresis, multiple key rollover electronics, and handshaking logic to interface asynchronously with any standard 8-bit microprocessor such as the 8080. Off chip is only an RC network for the purpose of setting the oscillator frequency.     

A single-chip fingerprint sensor and identifier

A chip architecture that integrates a fingerprint sensor and an identifier in a single chip is proposed. The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. The sensing element is built above the processing element in each pixel. The chip architecture realizes a wide-area sensor without a large increase of chip size and ensures high sensor sensitivity while maintaining a high image density. The sensing element is covered with a hard film to prevent physical and chemical degradation and surrounded by a ground wall to shield it. The wall is also exposed on the chip surface to protect against damage by electrostatic discharges from the finger contacting the chip. A 15×15 mm² single-chip fingerprint sensor/identifier LSI was fabricated using 0.5-μm standard CMOS with the sensor process. The sensor area is 10.1×13.5 mm². The sensing and identification time is 102 ms with power consumption of 8.8 mW at 3.3 V. Five hundred tests confirmed a stranger-rejection rate of the chip of more than 99% and a user-rejection rate of less than 1%     

Design and characterization of novel read-out systems for a capacitive DNA sensor

This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.     

A smart capacitive angle sensor

This paper presents a smart capacitive angle sensor suited for automotive and industrial use. To comply with tough constraints of such applications in terms of environmental conditions, unit costs, and physical size, a fully integrated solution is mandatory. However, the limitations and capabilities of a single mixed-signal integrated circuit have considerable impact not only on the hardware architecture of the digital and analog system components, but also on the feasible measurement algorithm. A thorough investigation of all major nonlinear effects leads to an accurate system-level model of the sensor which is used to design a robust and reliable fully integrated sensor system capable of handling signal offset and amplitude variations. In addition, the proposed system recognizes and reacts on electromagnetic disturbances. Measurements taken from a final prototype comply with the simulation results.     

A polyimide-based capacitive humidity sensor

The design of a relative humidity sensor is studied in which the principle of operation is based on the change of dielectric constant of a thin film of polyimide. The design of the sensor is established in such a way that it would be suitable for an integrated-circuit type of fabrication. The studies have shown that the experimental data are described well by the use of the Looyenga equation for dielectric constant behavior coupled with the Dubinin equation to describe the absorption as a function of relative humidity.     

A digital readout technique for capacitive sensor applications

The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3-μm CMOS technology. Detection of percent differences of <0.5% on 20-100-fF capacitors has been successfully demonstrated     

A capacitive tactile sensor array for surface texture discrimination

This paper presents a silicon MEMS based capacitive sensing array, which has the ability to resolve forces in the sub mN range, provides directional response to applied loading and has the ability to differentiate between surface textures. Texture recognition is achieved by scanning surfaces over the sensing array and assessing the frequency spectrum of the sensor outputs.     

A 16-channel capacitance-to-period converter for capacitive sensor applications

An electronic system able to read out arrays of up to sixteen different capacitive type sensors is presented. The output signal of the readout is a square wave signal, with oscillation period linearly modulated by the respective sensor capacitance under measurement. Components such as charge/discharge current control unit, a multiplexing unit and a bandgap voltage reference are integrated on chip, to obtain a stable and linear readout system for multiple sensors of variable types and capacitance ranges. The ASIC was designed and fabricated in AMS 0.35???m CMOS technology and was hosted on a PCB together with a supervising microcontroller, which is programmed to produce ratiometric measurements using reference capacitances to minimise parasitic effects. Finally, a USB interface undertakes the task of communicating the results to a personal computer. Characterization of the system was performed using (a) discrete capacitances and (b) capacitive pressure sensors. The system was evaluated in a capacitance range of 10?C140?pF exhibiting high linearity (r?=?0.9954) with sensitivity of 0.062???s/pF when tested using in-house made capacitive pressure sensors.     

一种适用于传感器接口电路中电容型SAR结构ADC的修调技术

本文提出了一种针对电容型逐次逼近型模数转换器（ADC）的修调技术及实现算法,采用了该技术的ADC可作为传感器和微控制器之间的接口电路使用。其特点在于这种修调后的电路可以在不需要单独的校正周期,也不需要附加复杂的校正功能,只需要通过对电容阵列的微调,就可以达到12-bit的分辨率。这种技术具有功耗和面积的优势,适合用于对功耗和成本较为敏感的电池供电系统,例如传感器网络结点。本文在0.5μm 2P3M CMOS工艺下设计了一个12bit分辨率的ADC原型电路,在2-5V电源电压下,200KHz采样速度下,其功耗仅为300μA。     

CMOS电容式湿度传感器特性研究

提出了一种CMOS电容式湿度传感器特性研究方案.研究所用的微电容湿度传感器由标准CMOS工艺结合MEMS 后处理技术加工而成.为了测试湿度传感器的响应时间,设计了一种响应时间测试装置.测试结果表明,该电容式湿度传感 器在相对湿度25％～95％的范围内具有较好的线性度;其回滞在75％RH时达到最大,为2％ RH;该传感器...     

A monolithic capacitive pressure sensor with pulse-period output

A new microminiature monolithic capacitive pressure transducer (CPT I) is 20 times more sensitive than piezoresistive strain-gauge pressure transducers, requires one percent of the power, and can be batch fabricated through current integrated circuit technology. A second device (CPT II) incorporates bipolar signal-processing electronics on the same silicon chip to produce a low-duty-cycle pulse-mode output with period related to pressure. This output format helps to re-solve the problem of shunting between leads, which is one of the principal causes of long-term drift in piezoresistive transducers designed for implantable medical applications. Because this device uses capacitance change as a transductional mechanism rather than piezo-resistivity, it is not susceptible to drift caused by temperature variations in the piezoresistive coefficient. Optimization for totally implantable biomedical applications places special emphasis on small size, high sensitivity, improved long-term baseline stability, and greatly reduced power consumption. These properties are also important for a wide range of pressure-sensing applications-from automotive to general industrial use.     

A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm/spl times/20 mm/spl times/1.2 mm and the sensor area is 19.2 mm/spl times/15 mm. The size of the prototype cell is now 60 /spl mu/m/spl times/60 /spl mu/m at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.     

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during long-time use. The scheme consists of an automatic calibration circuit for each pixel and a calibration control circuit for the pixel array. The calibration is executed by adjusting variable capacitance in each pixel to make the sensor signals of all pixels the same. The calibration control circuit selects the pixels in parallel, and calibrates all pixels in a short time. The scheme was applied to a fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process, and clear fingerprint images were obtained even for a degraded surface condition. This confirms that the scheme is effective for capturing consistent clear images during long-time use.     

A novel method of optical detection using a capacitive device

This paper describes a new method of optical detection, which essentially involves the measurement of the change in charge spectrum of MOS capacitors with incident light. It also suggests a symmetric insulator-semiconductor-insulator (ISI) structure for an efficient optical detector     

A high-speed capacitive humidity sensor with on-chip thermal reset

This paper reports a high-speed capacitive humidity sensor integrated on a polysilicon heater. A response time of 1.0 s and a sensitivity of 30.0 fF/%RH have been obtained. High speed is achieved using multiple polyimide columns having diameters of a few microns and allowing moisture to diffuse into them circumferentially. Using structures that eliminate the air-gap capacitance between the columns, the simulated sensor output drifts by only 1% when the relative dielectric constant in the air region changes from 1 to 10. A polysilicon heater is used to measure relative humidity levels >80% RH. An accuracy of ±3% RH has been obtained using this method, with measurement errors of ±0.5°C and ±2% RH in temperature and relative humidity, respectively. The heater also reduces the recovery time after wetting, enables the sensor to recover from contamination and aging, and allows the sensing film to be reset on demand during self-test protocols     

A 600-dpi capacitive fingerprint sensor chip and image-synthesistechnique

This paper examines the possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of 64×256 sensing cells (chip size: 2.7×10.8 mm²). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic capacitances. Thus, the reduced sensing-capacitor size enables a high resolution of 600 dpi, even using a conventional 0.6 μm CMOS process. The partial fingerprint images captured are synthesized into a full fingerprint image with an image-synthesis algorithm. The problems and possibilities of this image-synthesis technique are also analyzed and discussed     

A fingerprint sensor based on the feedback capacitive sensingscheme

This paper introduces a single-chip, 200×200-element sensor array implemented in a standard two-metal digital CMOS technology. The sensor is able to grab the fingerprint pattern without any use of optical and mechanical adaptors. Using this integrated sensor, the fingerprint is captured at a rate of 10 F/s by pressing the finger skin onto the chip surface. The fingerprint pattern is sampled by capacitive sensors that detect the electric field variation induced by the skin surface. Several design issues regarding the capacitive sensing problem are reported and the feedback capacitive sensing scheme (FCS) is introduced. More specifically, the problem of the charge injection in MOS switches has been revisited for charge amplifier design     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

Laser THz emission microscope as a novel tool for LSI failure analysis

We have proposed and developed a novel technique for a non-contact inspection of defective interconnections in an LSI chip using a laser terahertz emission microscope (LTEM). The LTEM measures the THz emission images of an LSI chip by scanning it with fs laser pulses. When a fs laser pulse irradiates a p–n junction in an LSI chip, transient photocurrent flows into interconnections resulting in the emission of the THz pulse into free space. We investigated the characteristics of the THz emissions from simple test element group samples which consist of p–n junctions connected to metal lines. It was found that the metallic lines connected to photo-excited p–n junctions worked as THz emission antennae which enhance the emission efficiency of THz pulses near their resonant frequencies corresponding to the line lengths. This result indicates that THz emission signals from p–n junctions in circuits strongly depend on the structure of the interconnections. We show the successful results on the inspection of defective interconnections in MOSFET devices and C7552 ISCAS’85 benchmark circuits using LTEM. By comparing the THz emission images between a normal circuit and a defective one, it is possible to identify the p–n junctions connected to the defective interconnections without electrical contacts.     

CMOS based capacitive sensor laboratory-on-chip: a multidisciplinary approach

In this paper, we review the recent advances of CMOS-based capacitive sensors for Lab-on-chip (LoC) applications. LoC design is a multidisciplinary approach of adapting classical biochemical assays to a miniaturized platform by exploiting advances in microelectronic and microfluidic technologies. By offering low cost and integrated devices, CMOS based LoCs could be amenable to a large number of biological and biochemical assays for disease diagnostics and biotechnology in the near future. While an exhaustive, all-encompassing review of CMOS-based LoCs is beyond the scope of this review, we have focused on the design and implementation of CMOS-based capacitive sensor LoCs for the most important biochemical applications. For each application, the corresponding biochemical sensing layer, interface circuit and microfluidic packaging technique are discussed based on the recent literature studies.