Compact distributed RLC interconnect models-Part II: Coupled linetransient expressions and peak crosstalk in multilevel networks

For pt. I see ibid., vol. 47, no. 11, (Nov. 2000). Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled interconnects are rigorously derived. These new distributed rlc models reveal that peak crosstalk voltage is over 60% larger for 3 GHz high-speed interconnects than predicted by current distributed RC models. Simplified forms of the compact models enable physical insight and accurate estimation of peak crosstalk voltage between two and three distributed RLC interconnects     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.     

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.     

Exact moment matching model of transmission lines and applicationto interconnect delay estimation

Moment matching methods are widely used in delay estimation of interconnects modeled as transmission line networks. In this paper, we analyze the contribution of a transmission line to the moments of a resistor-transmission line-capacitor (R-T-C) network and provide a method to form a lumped moment matching model of the line. When the transmission lines are replaced by their pth order moment matching models, the network is transformed into a lumped R-L-C network such that these two networks have identical moments up to the order of p for each corresponding output node voltage. We also provide a recursive formula to compute the moments of the R-L-C network so that the moment matching techniques can be efficiently used in the delay estimation     

Modelling noise and delay in VLSI circuits

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.     

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects

We introduce a Nyquist stability analysis of coupled mixed CNT bundle (MCB) for sub-threshold interconnects. In this analysis, the dependence of relative stability of sub-threshold MCBs with specific and probabilistic distribution of CNTs, on the geometry and probability of metallic CNTs, has been obtained. Using the proposed ABCD model and Nyquist stability criterion for sub-threshold MCBs, we show that, by increasing the diameter of each individual CNT and the length of MCB, the sub-threshold MCB interconnect system becomes more stable, while a densely packed MCB reduces the relative stability. Moreover, the crosstalk impact results in the greater stability of sub-threshold MCB system in comparison to a single interconnect. The crosstalk delay of MCB and composite Cu-MWCNT interconnects is also compared at various lengths. This is, so far, the first instance that such an analysis has been presented for coupled sub-threshold MCB interconnects.     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique

This paper presents an accurate and efficient model for the transient analysis of multiwall carbon nanotubes (MWCNT) using finite-difference time-domain (FDTD) method. The proposed model can be essentially used to analyze the functional and dynamic crosstalk effects of coupled-two MWCNT interconnect lines. Using the proposed model the voltage and current can be accurately estimated at any point on the interconnect line and furthermore, the model can be extended to coupled-n interconnect lines with a low computational cost. Crosstalk induced propagation delay, peak voltage, and its timing instance are measured using the proposed model and validated by comparing it to the HSPICE simulations. Over a random number of test cases it is observed that the average error in estimating the noise peak voltage on a victim line is less than 1%. The proposed model is extremely useful for accurate estimation of crosstalk induced performance parameters of MWCNT interconnects.     

Crosstalk-affected delay analysis in nanometer technologies

This article presents a detailed analysis of the crosstalk-affected delay of coupled interconnects considering process variations. We utilise a distributed RC-π model of the interconnections to accurately model process variations. In particular, we perform a detailed investigation of various crosstalk scenarios and study the impact of different parameters on crosstalk delay. Although accounting for the effect of correlations among parameters of the neighbouring wire segments, statistical properties of the crosstalk-affected propagation delays are characterised and discussed. Monte Carlo-based simulations using Spice demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay in the presence of crosstalk.     

两相邻耦合RC互连的串扰效应及其抑制

随着深亚微米设计的发展,互连线串扰变得更加严重.文中分析了深亚微米集成电路设计中对两相 邻耦合RC互连串扰的成因,论述了在设计中抑制串扰一般方法.     

An improved RC model for VLSI interconnects with applications to buffer insertion

A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the π-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.     

Capacitance coupling immune, transient sensitive accelerator forresistive interconnect signals of subquarter micron ULSI

This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.     

Analysis of lossy multiconductor transmission lines using theasymptotic waveform evaluation technique

A method is described for the transient analysis of lossy coupled transmission line networks with nonlinear elements. The method combines the asymptotic waveform evaluation technique with a piecewise decomposition algorithm. Two to three orders of magnitude speedup can be achieved relative to previously published methods with comparable accuracy. The method is useful for delay and crosstalk simulation of high speed VLSI interconnects     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

Moment models of general transmission lines with application tointerconnect analysis and optimization

In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute these mean values efficiently. By using such models and moment matching techniques, interconnects modeled as transmission line networks can be efficiently simulated. In addition, by using moment sensitivities, we demonstrate that wire sizing optimization can be carried out for layout design     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems