A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique

This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8×1.4 mm² in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200 MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4 MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49 dB–70.71 dB while consuming of 112 mW at a supply voltage of 1.1 V.     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm² and dissipates 909 mW from a 1.8 V supply.     

A sub-sampling 4.25 GS/s 3-bit flash ADC with asymmetric spatial filter response

A sub-sampling 3-bit 4.25 GS/s flash ADC with a novel averaging termination technique—asymmetric spatial filter response—in 0.13 um CMOS for impulse radio ultra-wideband (IR-UWB) receiver is presented. In this design, a track and hold (T/H) circuit with self-biased buffer is used to compensate the degradation in amplitude when frequency increases to giga Hz. Averaging termination technique using asymmetric spatial filter response is proposed to relieve the termination offset of the flash ADC. A revised encoder scheme is adopted to solve the problem of different propagation delay. The measurement results reveal that the SFDR and SNDR of the ADC are 26.3 dB and 18.4 dB, respectively, even the input signal frequency is 4.2 GHz. INL and DNL are measured improved to 0.11LSB and 0.18LSB, respectively, when asymmetric spatial filter is used. The power of ADC is 63 mW and the active area is 0.49×0.72 mm². The ADC achieves a figure of merit (FoM) of 2.2 pJ/conversion-step.     

An 8-bit 12.5-GSample/s SiGe ADC

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm² and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process.     

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65 nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07 mm². The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60 dB, a spurious free dynamic range of 73.35 dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85 mW at a 1.1 V supply and achieves a figure-of-merit of 51 fJ/conversion-step.     

A 10-bit 250-MS/s binary-weighted current-steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.     

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm², and consumes 518 mW at 1.8 V supply.     

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10⁻⁹. The total active area is 0.21 mm² and the ADC consumes 76 mW from a 1.2-V supply.     

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 times 0.7 mm². The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than plusmn1.07 LSB, and the differential nonlinearity is less than plusmn0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.     

一种全集成8位2.16 GS/s SAR ADC

设计了一种8位2.16 GS/s四通道、时间交织逐次逼近型模数转换器(TI-SAR ADC)。单通道SAR ADC采用数据环、异步时钟环的双环结构实现高速工作。采用带复位开关的动态比较器缩短量化时间,提高比较精度。结合反向单调切换时序,逐步增大共模电压,提升量化速度。基于55 nm CMOS工艺设计,后仿真结果表明,在1.2 V电源电压下,该TI-SAR ADC消耗 42.6 mA 电流,在奈奎斯特输入频率下,FOM值为212 fJ/(conv.step),信噪失真比(SNDR)为42.7 dB,无杂散动态范围(SFDR)为53 dB。芯片整体版图面积为3.4 mm²。     

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm², and the ADC consumes 6 mW from a 1.2-V supply     

A 1.2?V 10-bit 60-MS/s 23?mW CMOS pipeline ADC with 0.67?pJ/conversion-step and on-chip reference voltages generator

A 1.2?V 10-bit 60?MS/s pipeline Analog-to-Digital Converter (ADC), fabricated in a 130?nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage supply requirements. Special attention has been paid to the reduction of the power consumption using a thorough design methodology. The converter only consumes 23?mW including on-chip reference voltages and bias current generators. The differential and integral nonlinearity of the ADC are below 0.60 and 0.61 LSBs, respectively. The pipeline converter achieves an effective resolution above 9 bits along the Nyquist bandwidth, and obtains 0.67?pJ energy consumption per conversion, making it one of the most energy-efficient 10-bit video-rate pipeline ADC reported to date.     

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.     

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-μm CMOS process with power dissipation 21-mW, signal-to-noise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) −75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.