On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35 /spl mu/m CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original /spl sim/2 kV to >8 kV by using this proposed ESD protection circuit.     

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.     

基于STNMOS的混合电压I／O接口ESD保护

混合电压I／O接口的静电放电（electrostaticdischarge,ESD）保护设计是小线宽工艺中片上系统（SoC）设计的主要挑战之一。混合电压I／O接口的片上ESD保护既要避免栅氧可靠性问题,又要防止不期望的泄漏电流路径产生。这篇论文讨论了基于堆叠NMOS（Stacked—NMOS,STNMOS）的混合电压I／O接口的ESD保护设计构思和电路实现,通过不同ESD保护设计方案的比较,提出了一个最有效的保护方案。     

Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors

S I/O buffer has. The design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by～34% with respect to the product of power consumption and speed.     

新型薄栅氧混合电压I/O缓冲器

This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS process.This mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer has.The design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ～34% with respect to the product of power consumption and speed.     

ESD protection design for I/O libraries in advanced CMOS technologies

There are several approaches for ESD protection of integrated circuits. This paper provides practical guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR, MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special CDM ESD protection solutions are not considered.     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robustness under the positive-to-V_SS (PS-mode) ESD test, which is the most critical ESD-test pin combination. With a silicon-controlled rectifier (SCR) between the I/O pad and V_SS, the clamping voltage along the PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.     

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications.     

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.     

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration

We demonstrate that NMOS transistors stacked in a cascode configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. Circuits for gate voltage modulation were added to ensure uniform finger triggering of the fully silicided device. Layout and circuit rules were developed to avoid parasitic breakdown paths.     

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R_ON * C_ESD, I_CP/C_ESD, V_HBM/C_ESD, and I_CP/A_Layout) of ESD protection diodes with new proposed layout styles can be successfully improved.     

具有静电放电保护特性的高阻抗缓冲放大器输入

PH值(酸碱度)和生物电位等特性测量需要高阻抗缓冲放大器。虽然几家半导体制造商提供具有较低偏置电流和偏移输入电流的放大器IC,但把传感器电缆连接到放大器电路可能会遭到ESD(静电放电)损害。图1示出了一种并不令人满意的ESD保护方法。电阻器R1限制了ESD事件的放电电流,二极管D1A和D1B把放大器IC1的输入箝位到它的     

多指条nMOSFET抗ESD设计技术

利用多指条nMOSFET进行抗ESD设计是提高当前CMOS集成电路抗ESD能力的一个重要手段，本文针对国内某集成电路生产线，利用TLP(Transmission Line Pulse)测试系统，测试分析了其nMOSFET单管在ESD作用下的失效机理，计算了单位面积下单管的抗ESD(Electro Static Discharge)能力，得到了为达到一定抗ESD能力而设计的多指条nMOSFET的面积参数，并给出了要达到4000V抗ESD能力时保护管的最小面积，最后通过ESDS试验进行了分析和验证。     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected