Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.     

Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms

We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.     

Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs

This paper presents the design of a soft IP for JPEG compression targeted for high performance in a FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The JPEG compressor architecture was designed in a hierarchical and modular fashion and the details of the global architecture and of its modules are presented in this paper. A modular and strictly structural VHDL design is followed to develop the JPEG compressor soft IP. The VHDL codes were synthesized to Altera and Xilinx FPGAs. Synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor is able to compress 39.8 millions of pixels per second when mapped onto an Altera FLEX 10KE FPGA. Our JPEG soft IP mapped to FLEX 10KE low cost FPGA is able to compress 115 images per second in SDTV resolution (720 × 480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate of 30 fps, once mapped to the FLEX 10KE FPGA device.     

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

This work reports an efficient and compact FPGA processor for the SHA-256 algorithm. The novel processor architecture is based on a custom datapath that exploits the reusing of modules, having as main component a 4-input Arithmetic-Logic Unit not previously reported. This ALU is designed as a result of studying the type of operations in the SHA algorithm, their execution sequence and the associated dataflow. The processor hardware architecture was modeled in VHDL and implemented in FPGAs. The results obtained from the implementation in a Virtex5 device demonstrate that the proposed design uses fewer resources achieving higher performance and efficiency, outperforming previous approaches in the literature focused on compact designs, saving around 60% FPGA slices with an increased throughput (Mbps) and efficiency (Mbps/Slice). The proposed SHA processor is well suited for applications like Wi-Fi, TMP (Trusted Mobile Platform), and MTM (Mobile Trusted Module), where the data transfer speed is around 50 Mbps.     

一个基于形式化方法的系统安全性建模分析实例研究

随着安全关键性系统的日益复杂,如何提高安全关键系统的安全性成为急需解决的问题.基于形式化模型的复杂系统设计与分析是一种重要的安全性分析方法.本文工作对AIR6110标准中的机轮刹车实例系统进行了基于形式化方法的安全性分析研究,包括:在系统模型设计层级对机轮刹车系统(WBS)的架构进行层次化分析,将自然语言描述的WBS系统功能用形式化语言(AADL的子集SLIM)进行严格的建模描述,消除AIR6110标准中自然语言描述存在的需求语义的二义性,从而建立了WBS系统的形式化模型;考虑系统可能发生的故障并设计多种类的故障模式,基于这些故障模式对建立的形式化功能模型进行失效行为语义的扩展,然后对获得的扩展系统模型进行安全性分析.实例分析论证了基于模型的安全性分析方法在工业系统中的有效性和实用性.     

Designing fault-tolerant techniques for SRAM-based FPGAs

FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.     

基于VHDL高级综合的条码阅读预处理器的FPGA设计

文中定义了条码阅读处理器的功能，给出其ＶＨＤＬ语言的行为源描述，讨论了在ＶＨＤＬ高级综合系统ＨＬＳ／ＢＩＴ的支持下面向ＦＰＧＡ，从算法级行为描述开始，自顶向下地进行条码阅读预处理器的设计过程，从中可见，ＶＨＤＬ高级综合和ＦＰＧＡ的结合，是一种简化设计复杂度，提高设计时效的ＡＳＩＣ的简便方法。     

Reconfiguring one-time programmable FPGAs

Field-programmable gate arrays can suffer from a variety of faults, ranging from wire anomalies and defects to inoperative programmable connections. The solution to these faults depends on whether or not we are dealing with a reprogrammable FPGA or a one time programmable (OTP) FPGA. To correct faults, developers can reconfigure FPGAs such as those made by Xilinx and Altera by reprogramming. These devices can be programmed many times, for different designs and applications. Correcting faults in OTP FPGAs, such as those made by Actel is more difficult. For one thing, OTP FPGAs are based on antifuses. With an antifuse, the FPGAs configuration information has an initial (default) value that can be changed, but once changed cannot be restored. Therefore, the procedures to bypass faulty cells or faulty routing in an OTP FPGA must meet more stringent requirements than for reprogrammable FPGAs. The “Reconfiguration Approaches” sidebar describes two methods other researchers have tried. This article describes our approach to reconfiguring OTP FPGAs. We explain how we determine if reconfiguration is feasible, the algorithms we used, and the results of our experiments on a generic OTP FPGA model and a generic detail router     

用XYZ／E语言描述和验证硬件的行为

本文考虑用时态逻辑语言ＸＹＺ／Ｅ描述硬件行为的可行性．作为实例，用ＸＹＺ／Ｅ语言描述了一个基于微处理器的容错计算机系统，这种描述可以在ＸＹＺ系统上执行，从而可对系统进行模拟．特别有意义的是利用ＸＹＺ／ＶＥＲＩ验证子系统对所期望的性质进行了形式化证明．本文还将ＸＹＺ／Ｅ描述与相应的ＶＨＤＬ（ＶＨＳＩＣｈａｒｄｗａｒｅｄｅｓｃｒｉｐｔｉｏｎｌａｎｇｕａｇｅ）描述进行了比较．从中可以看出时态逻辑语言的描述具有其独特的优点.     

芯片开发功能验证的形式化方法

在芯片设计领域,采用模型驱动的FPGA设计方法是目前较为安全可靠的一种方法.但是,基于模型驱动的FPGA设计需要证明FPGA设计模型和生成Verilog/VHDL代码的一致性.同时,芯片设计的正确性、可靠性和安全性也至关重要.目前,多采用仿真方法对模型和代码的一致性进行验证,很难保证设计的可靠性和安全性,并存在验证效率低、工作量大等问题.本文提出了一种新型验证设计模型和生成代码一致性的方法.该方法利用MSVL语言进行系统建模,并通过模型提取命题投影时序逻辑公式描述的系统的性质,通过统一模型检测的原理,验证模型是否满足性质的有效性.进而,应用信号灯控制电路系统作为验证实例,对验证方法做了检验和说明.     

Dependable, intelligent voting for real-time control software

An intelligent and dependable voting mechanism for use in real-time control applications is presented. Strategies proposed by current safety standards advocate N-version software to minimize the effects of undetected software design faults (bugs). This requires diversity in design but presents a problem in that truly diverse code produces diverse results; that is, differences in output values, timeliness and reliability. Reaching a consensus requires an intelligent voter, especially when non-stop operation is demanded, e.g. in aerospace applications. This paper, therefore, firstly considers the applicable safety standards and the requirements for an intelligent voter service. The use of replicated voters to improve reliability is examined and a mechanism to ensure non-stop operation is presented. The formal mathematical analysis used to verify the crucial behavioural properties of the voting service design is detailed. Finally, the use of neural nets and genetic algorithms to create N- version redundant voters, is considered.     

VHDL语言在FPGA中的应用

本文讨论了用VHDL语言进行FPGA设计的方法,简单介绍了VHDL语言的基本概念以及FPAG的设计流程,并举例说明了如何编写可综合的VHDL代码,使用Altera公司的MAX+PLUSII10.2开发软件进行功能仿真并给出仿真波形。     

Dependable design technique for system-on-chip

A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.     

基于Handel—C语言的FPGA设计

对于以ISO／ANSI—C为基础的程序设计语言Handel—C，可利用Celoxiea DK设计工具将Handel—C的源代码编译成能直接针对FPGA目标的网表(Netlist)，而无需VHDL／Verilog的中间步骤，最后利用FPGA布线工具直接将Netlist下载到FPGA上。文中在分析Handel—C语言的FPGA开发流程的基础上，将Handel—C与VHDL设计进行对比分析，揭示了Handel—C在电路算法级设计方面的优势，而且设计效率也大大提高。     

一种高速ZBTSRAM控制器设计

FPGA已经在雷达领域得到了广泛应用,然而其内部存储容量通常无法达到系统需求,因此必须为FPGA配置外部高速存储器。本设计采用两片高性能ZBTSRAM作为乒乓缓冲区交替工作,最高访问速率可达133MHz,使FPGA片外总存储容量达到32Mbit,满足设计要求。由于ZBTSRAM具有特殊的访问时序,必须使用FPGA的内部数字时钟管理模块DCM对时钟的相位进行精确控制,同时还要使用时序约束高级设计技术调整控制器的输入输出延时特性,使该控制器能够顺利地在FPGA内部信号处理系统和ZBT芯片之间完成高速数据交换。经过上述优化设计,采用VHDL代码编写可综合代码完成布线,目前该控制器已经成功地在某雷达导引头信号处理机中获得应用,验证了其有效性。     

基于VHDL语言的参数化设计方法

随着FPGA制造工艺的不断进步,越来越多的应用可以在FPGA中实现。虽然用于FPGA设计的VHDL语言具有很好的可移植性,但是FPGA芯片的可用资源不尽相同,因此对设计的规模进行参数化才能实现设计的可移植及充分利用FPGA的资源。此外,同一算法在不同的应用领域中,也会需要对其规模进行改变。设计的参数化是指只需要对参数进行设定就可以自动生成相应规模设计的技术。首先提出了一种基于综合工具的VHDL参数化设计方法,其次以多路奇偶校验生成器为例,详细说明了参数化的基本过程,最后在HMMer的FPGA实现中应用所提出的方法,从而实现对运算单元数量的控制。所提出的参数化方法具有操作简单、代码变动小、无需要第三方代码支持等优点。实验表明,该方法是VHDL设计中成本小、效果好的参数化设计方案。     

微小卫星星载计算机存储容错技术研究

结合南京航空航天大学小卫星研制课题,针对数据在星载计算机存储器存储的过程中,由于太空中辐射导致的单粒子翻转效应(SEU)使存储数据产生错误的现象,提出了采用纠检错技术对该小卫星存储模块进行设计的方法,与硬件系统相结合,实现小卫星数据存储系统容错。探讨了用VHDL语言实现纠错模块的方法,并最终用FPGA实现。此设计用modelsim进行了仿真测试,效果良好,同时在小卫星模拟仿真运行过程中,运行正常,多次得到了验证。