图像编解码中IDCT的FPGA实现

在MPEG解码电路中,IDCT是整个解码过程中运算量最大的一部分。介绍一种基于查找表(LUT)实现IDCT的方案,并用Verilog语言在FPGA芯片上得到了实现。     

基于单片机的FPGA并行多任务配置

介绍基于SRAM LUT结构的FPGA器件的上电配置方式;并以ALTERA公司ACEXlK系列器件为例,提出了一种利用单片机AT89C52、FLASH存储器对FPGA进行并行配置及实现多任务电路结构配置的方法.     

基于新型BIST的LUT测试方法研究

针对FPGA内部的LUT资源覆盖测试,提出一种新型BIST的测试方法。通过改进的LFSR实现了全地址的伪随机向量输入,利用构造的黄金模块电路与被测模块进行输出比较,实现对被测模块功能的快速测试,并在Vivado 2018.3中完成了仿真测试。通过ATE测试平台,加载设计的BIST测试向量,验证结果与仿真完全一致,仅2次配置即可实现LUT的100%覆盖率测试。此外,还构建了LUT故障注入模拟电路,人为控制被测模块的输入故障,通过新型BIST的测试方法有效诊断出被测模块功能异常,实现了准确识别。以上结果表明,该方法不仅降低了测试配置次数,而且能够准确识别LUT功能故障,适用于大规模量产测试。     

一种基于AND-LUT的混合FPGA结构

提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.     

一种基于AND-LUT的混合FPGA结构

提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.     

SRAM型FPGA单粒子翻转故障定位注入研究

针对SRAM型FPGA用户设计电路可靠性评测问题,提出了一种基于FPGA配置资源位置的模拟FPGA单粒子翻转故障的定位注入方法。分别从SRAM型FPGA中的配置逻辑资源与用户逻辑资源两个方面对此方法进行了详细介绍,并且通过对LUT与BRAM两种资源的故障注入试验说明了此方法的有效性。对故障注入方法、故障注入系统、故障注入试验进行了介绍,说明了故障定位注入方法能够对用户设计电路中用到的关键资源进行测试,资源覆盖率高、耗时短,为针对大量配置逻辑资源进行故障定位注入,实施反复测试提供了时效前提,具有很强的实用性。     

LUT尺寸对FPGA面积和延迟影响的理论分析

在分析隔离岛式FPGA结构的基础上,提出了基于LUT的面积和延迟模型,用于分析LUT尺寸对FPGA面积和性能的影响.结果表明利用计算模型得到的最佳LUT尺寸与实验结论一致:4-LUT获得最好的面积有效性,5-LUT获得较好的延迟.     

一种基于LUT的改进FIR滤波器的设计

目前,在基于FPGA的滤波器设计中,仍然不能同时很好地减小面积消耗和传输延时.分布式算法(DA)由于具有节省硬件资源的优势而被广泛应用于FIR滤波器设计,但在某些系统的设计中,资源消耗和传输延迟仍然不能满足要求.针对分布式算法存在的问题,设计了一种基于LUT的改进FIR滤波器,在相同的滤波要求下,面积消耗和传输延迟更低.在QUARTUS Ⅱ上分别对DA算法实现的滤波器及改进LUT结构实现的滤波器进行综合仿真,结果表明,改进LUT结构实现的滤波器节省近15%的面积,而且具有更低的延时.     

拆分粒度对FPGA可拆分逻辑结构性能的影响

可编程逻辑块是现场可编程门阵列(FPGA)的核心组成部分(主要由查找表(LUT)和寄存器构成),它的内部结构设计一直是研究的重要方向。可拆分逻辑结构给电路实现带来了灵活性。本文以6-LUT作为研究对象,从拆分粒度的角度出发,研究不同的可拆分因子(N=1,2,3,4)对电路性能带来的影响。仿真实验基于开源的FPGA CAD工具(ABC和VPR)和VPR测试电路集,实验结果表明：a) 不同可拆分因子对电路关键路径延时影响不大;b) 可拆分因子为2时,电路使用资源的面积和面积-延时积均最小,呈现更好的性能。     

基于FPGA的在线可写CAM存储器设计

简述了CAM存储器(Content Addressable Memory)的主要应用,讨论了采用可编程器件FPGA设计CAM的一般方法和优缺点,针对FPGA设计的CAM不易在线写入的问题,提出了利用FPGA中查找表LUT设计存储单元,实现CAM内容在线可写的新方法。详细论述了基于Xilinx公司最新FPGA设计实现在线可写CAM的技术,通过设计实例验证了方法的实用性,分析了资源消耗和访问速度,表明该方法设计的CAM资源利用率较高、访问速度快、设计方法容易、易于扩展,能够满足内容在线可写的应用要求。     

Filter Lookup Table Method for Power Amplifier Linearization

This paper presents a new method of digital adaptive predistortion for linearization of power amplifiers (PAs) exhibiting memory effects. The predistorter (PD) device consists of a lookup table (LUT) gain followed by a codebook of filters addressed by the index of the LUT. The adaptation is derived from direct learning for the LUT gains and indirect learning for the filter coefficients. We compared our results with those of two reference methods: a simple LUT system (with direct learning) and a memory polynomial system (with indirect learning). The performances of the new approach lie between those of the two reference methods in terms of adjacent channel power regrowth and error vector magnitude. The LUT is the less complex of the three methods, but it is a memoryless system, and it cannot correct the memory effects in the PA. The memory polynomial PD is more powerful, but its complexity is very high. The new technique, due to the addition of filters to the LUT, has possibilities to compensate not only for the nonlinearity but also for the memory effects in the PA, and it is one order of magnitude less complex than the memory polynomial system     

Current-Based Testing,Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

This paper presents a method for operational testing of a memristor-based look-up table (LUT) memory block. In the proposed method the deterioration of the memristors (as storage elements of a LUT), is modeled based on the reduction of the resistance range, a phenomenon well known as reported in the technical literature. A quiescent current technique is used to diagnose the memristors when deterioration results in a change of state, thus leading to a fault. In addition to testing, the proposed method can be utilized also for continuous monitoring of the memristor deterioration in the LUT. The deterioration of the memristors is modeled using a simple yet accurate equivalent circuit. The proposed method is simulated using LTSPICE and extensive simulation results are presented for operational deterioration with respect to different features such as LUT dimension, range of memristance and MOSFET feature size. These results show that the proposed test method is highly efficient for testing and monitoring a LUT in the presence of deteriorating multiple memristors.     

基于多级查找表的VLD设计及其状态机的优化

采用多级查找表的VLD方法具有快速、节省存储器空间等特点,因而在各种数字视频和图像解码器中得到了广泛的应用,本文详细地讨论了多级查找表及其状态机的设计和优化,并推导出了求LUT表项数和FSM状态数的具体公式,文中以MPEG1为数值样例,证明了该算法的正确性。利用本文的结果,可以在硬件设计时充分地节约表项资源。     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.     

查找表联合记忆效应补偿技术的宽带自适应预失真算法

为了能够对记忆型功率放大器线性化处理,并能一定程度克服其记忆效应,该文介绍一种自适应数字预失真器。该数字预失真器采用查找表与记忆效应补偿技术相结合的方法,并且利用内插值方法有效减小了查找表幅度量化过程产生的误差。相比记忆多项式预失真器,这种预失真器的计算复杂度较小,却能够得到与其相近的线性化效果。基于功率放大器记忆多项式模型,利用OFDM(Orthogonal Frequency Division Multiplexing)宽带信号验证该文提出的预失真器对记忆型非线性功率放大器的良好线性化效果。     

Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs

This paper presents a scheme for designing a memristor-based look-up table (LUT) in which the memristors are connected in rows and columns. As the columns are isolated, the states of the unselected memristors in the proposed scheme are not affected by the WRITE/READ operations; therefore, the prevalent problems associated with nanocrossbars (such as the write half-select and the sneak path currents) are not encountered. Extensive simulation results of the proposed scheme are presented with respect to the WRITE and READ operations; its performance is compared with previous LUT schemes using memristors as well as SRAMs. It is shown that the proposed scheme is significantly better in terms of WRITE time and energy dissipation for both memory operations (i.e. WRITE and READ); moreover it is shown that the READ delay is nearly independent of the LUT dimension. Simulation using benchmark circuits for FPGA implementation show that the proposed LUT offers significant improvements also at this level.     

Optimization of EDGE terminal power amplifiers using memoryless digital predistortion

This paper describes a lookup-table (LUT)-based digital predistortion system usable for enhanced data for global system for mobile evolution (EDGE) handset transmitters. The system is memoryless and capable of improving average efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude. The obtainable efficiency at maximum linear output power is comparable, but at backoffs superior to commercial EDGE power amplifiers (PAs). Minimum system requirements on word length and LUT size have been investigated, which shows that a LUT having approximately 500 coefficients and a system word length of 13 bits are sufficient for EDGE. The proposed system is simple compared to basestation implementations comprising PA memory compensation and can be easily implemented in handsets in order to improve the overall system performance. The effects of antenna mismatch on system performance have been investigated     

基于FPGA的LFM信号匹配滤波的时域实现

为解决频域法实现信号匹配滤波时硬件开销较大的问题,采用时域法实现线性调频（LFM）信号的匹配滤波。设计了一款针对LFM信号的8阶分布式结构的时域匹配滤波器;利用FPGA的ROM宏模块构建查找表,实现分布式滤波算法;基于FPGA器件完成了滤波器的设计与集成。仿真结果显示,滤波器占用170个逻辑单元、109个寄存器、3K字节存储器,逻辑资源开销较小。与传统FIR结构的乘累加算法相比,分布式滤波算法运算速度更快。     

一种基于分离算法记忆效应的预失真技术

在文献[5]提出的分离算法的基础上，针对其中记忆效应的预失真提出了一种新的算法。该算法将查表法算法应用于频率域，较好的解决了有记忆高功率放大器中记忆效应引起的消极影响，因此可以有效的将有记忆的艘A系统转化为一个无记忆的艘A系统。最后，进行了仿真模拟，结果显示这种算法能有效的消除记忆效应的影响。     

An improved look-up table predistortion technique for HPA with memory effects in OFDM systems

It is well known that HPAs (High Power Amplifiers) are inherently nonlinear devices and many researches have focused on the predistortion for memoryless HPAs. However, memory effects of HPAs can no longer be ignored when communication systems have wider bandwidth. Memoryless predistortion techniques proposed previously seldom have satisfactory effectiveness for typical wideband applications such as OFDM (Orthogonal Frequency Division Multiplexing) systems. In this paper, an improved adaptive predistortion method called 2D LUT (2-dimension look-up table) with different accuracy levels is presented to linearize HPAs with memory effects. Simulation and experimental results show that 2D LUT implements excellent performance in mitigating the signal deterioration caused by memory effects, both rectifies the signal constellation distortion and suppresses the spectrum emission. Large scale matrix computation is also avoidable in these adaptive algorithms, which makes them feasible when a real-time system is necessary.