Demonstration of GaN MIS diodes by using AlN and Ga2O3(Gd2O3) as dielectrics

GaN MIS diodes were demonstrated utilizing AlN and Ga₂O₃(Gd₂O₃) as insulators. A 345 Å of AlN was grown on the MOCVD grown n-GaN in a MOMBE system using trimethylamine alane as Al precursor and nitrogen generated from a SVT RF N₂ plasma. For the Ga₂O₃(Gd₂O₃) growth, a multi-MBE chamber was used and a 195 Å oxide was E-beam evaporated from a single crystal source of Ga₅Gd₃O₁₂. The forward breakdown voltage of AlN and Ga₂O₃(Gd₂O₃) diodes are 5 and 6 V, respectively, which are significantly improved over 1.2 V from that of a Schottky contact. From the C–V measurements, both kinds of diodes showed good charge modulation from accumulation to depletion at different frequencies. The insulator/GaN interface roughness and the thickness of the insulator were measured with X-ray reflectivity.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

One transistor ferroelectric memory with Pt/Pb5Ge3O11/Ir/poly-Si/SiO2/Si gate-stack

One transistor ferroelectric nonvolatile memory with gate stack of Pt/Pb₅Ge₃O₁₁/lr/poly-Si/SiO₂ /Si was successfully fabricated. This device features a saturated memory window of 3 V at a programming voltage of higher than 3 V from C-V and I-V measurements. The memory window decays rapidly within 10 seconds after programming, but remains stable at 1 V for up to 100 h. The "on" and "off" state currents are greater than 10 μA/μm and less 0.01 pA/μm, respectively, at a drain voltage of 0.1 V     

Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy₂O₃) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, V_t,lin of 0.18 V for long-channel devices (L_g = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy₂O₃ cap layer is also maintained in the short-channel devices (with an L_g,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy₂O₃ cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy₂O₃ layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

磁控管用新型直热式稀土铪酸钆陶瓷阴极研究

为了提高大功率磁控管的输出功率,延长其使用寿命,采用难熔稀土氧化钆和过渡金属氧化铪制备大功率磁控管用新型直热式稀土铪酸钆陶瓷阴极,并对该阴极的热发射特性和寿命特性等进行了测试,热发射测试结果显示该阴极在1300℃ br即可提供0.1A/cm²发射电流密度,1600℃ br下可提供超过1.93A/cm²的发射电流密度.寿命实验结果显示,该阴极在1500℃ br,直流负载为0.5A/cm²的条件下,寿命已经超过4000h.最后,利用X射线衍射仪、扫描电镜、能谱分析仪、氩离子深度刻蚀俄歇电镜等设备分别对该阴极活性物质的分子结构,阴极表面微观形貌、元素成分及含量等进行了分析.结果表明,高温烧结合成了单一的铪酸钆物相,烧结过程中当一种Gd³⁺价稀土氧化钆掺入Hf⁴⁺价的过渡金属氧化铪时,会发生离子置换固溶,为了保持铪酸钆晶格的电中性,晶格中就会产生一个氧空位.当阴极在激活、老练、热发射测试时,会加速氧空位的生成,产生的氧空位越多,阴极表面导电性就会越好,这间接降低了逸出功,从而提高了阴极的热发射能力.     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

肖特基型β-Ga2O3日盲紫外光电探测器

本文制备并研究了肖特基型β-Ga₂O₃日盲紫外光电探测器.结果表明：通过脉冲激光沉积外延生长的β-Ga₂O₃的（-201）晶面 X射线衍射峰半高宽仅为36 arcsec,表现出了高的晶体质量;光暗条件下的I-V曲线显示所制备的器件具有明显的肖特基整流特性,在-5V偏压下暗电流保持在0.1nA量级,正向导通电压为1.5V;光电流谱显示器件在240nm处存在显著的峰值响应,并在260nm左右呈现陡峭的截止边,日盲紫外的带内带外抑制比达到1000.同时,也研究了不同掺杂对Ga₂O₃晶体质量的影响.     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Enhancement-mode power heterojunction FET utilizingAl0.5Ga0.5As barrier layer with negligibleoperation gate current for digital cellular phones

We have developed a novel enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) with a 5 nm thick Al_0.5Ga_0.5As barrier layer inserted between an In _0.2Ga_0.8As channel layer and an upper Al_0.2 Ga_0.8As electron supply layer. The Al_0.5Ga _0.5As barrier layer reduces gate current under high forward gate bias voltage, resulting in a high forward gate turn-on voltage (V _F) of 0.87 V, which is 170 mV higher than that of an HJFET without the barrier layer. Suppression of gate current assisted by a parallel conduction path in the upper electron supply layer was found to be also important for achieving the high V_F. The developed device exhibited a high maximum drain current of 300 mA/mm with a threshold voltage of 0.17 V. A 950 MHz PDC power performance was evaluated under single 3.5 V operation. An HJFET with a 0.5 μm long gate exhibited 0.92 W output power and 63.6% power-added efficiency with 0.08 mA gate current (I_g) at -48 dBc adjacent channel leakage power at 50 kHz off-center frequency. This I_g is one-thirteenth to that of the HJFET without the barrier layer. These results indicate that the developed enhancement-mode HJFET is suitable for single low voltage operation power applications     

Ferroelectric neuron integrated circuits using SrBi2Ta2O9-gate FET's and CMOS Schmitt-triggeroscillators

A pulse frequency modulation (PFM) type ferroelectric neuron circuit composed of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) and a CMOS Schmitt-trigger oscillator was fabricated on an SOI structure, in which SrBi₂Ta₂O₉ (SBT) was used as a ferroelectric gate material of the FET. It was found that the fabricated MFSFET showed a relatively good I_D-V_G (drain current versus gate voltage) characteristic with a hysteresis loop due to the ferroelectricity of the SBT film and that it acted as a synapse device with adaptive-learning function. It was also found that the output pulse height of the circuit was as high as the power supply voltage and that output pulse frequency was changed as the number of applied input pulses increased     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

Low Dit, thermodynamically stable Ga2O3-GaAs interfaces: fabrication, characterization, and modeling

Thermodynamically stable, low D_it amorphous Ga₂ O₃-(100) GaAs interfaces have been fabricated by extending molecular beam epitaxy (MBE) related techniques. We have investigated both in situ and ex situ Ga₂O₃ deposition schemes utilizing molecular beams of gallium oxide. The in situ technique employs Ga₂O₃ deposition on freshly grown, atomically ordered (100) GaAs epitaxial films in ultrahigh vacuum (UHV); the ex situ approach is based on thermal desorption of native GaAs oxides in UHV prior to Ga₂O₃ deposition. Unique electronic interface properties have been demonstrated for in situ fabricated Ga₂O₃-GaAs interfaces including a midgap interface state density D_it in the low 10¹⁰ cm^-2 eV^-1 range and an interface recombination velocity S of 4000 cm/s. The existence of strong inversion in both n- and p-type GaAs has been clearly established. We will also discuss the excellent thermodynamic and photochemical interface stability. Ex situ fabricated Ga₂O₃-GaAs interfaces are inferior but still of a high quality with S=9000 cm/s and a corresponding D_it in the upper 10¹⁰ cm^-2 eV^-1 range. We also developed a new numerical heterostructure model for the evaluation of capacitance-voltage (C-V), conductance-voltage (G-V), and photoluminescence (PL) data. The model involves selfconsistent interface analysis of electrical and optoelectronic measurement data and is tailored to the specifics of GaAs such as band-to-band luminescence and long minority carrier response time τ_R. We will further discuss equivalent circuits in strong inversion considering minority carrier generation using low-intensity light illumination     

Plasma-Enhanced Atomic Layer Deposition of Amorphous Ga2O3 for Solar-Blind Photodetection

Wide-bandgap gallium oxide (Ga₂O₃) is one of the most promising semiconductor materials for solar-blind (200 nm to 280 nm) photodetection. In its amorphous form, amorphous gallium oxide (a-Ga₂O₃) maintains its intrinsic optoelectronic properties while can be prepared at a low growth temperature, thus it is compatible with Si integrated circuits (ICs) technology. Herein, the a-Ga₂O₃ film is directly deposited on pre-fabricated Au interdigital electrodes by plasma enhanced atomic layer deposition (PE-ALD) at a growth temperature of 250 °C. The stoichiometric a-Ga₂O₃ thin film with a low defect density is achieved owing to the mild PE-ALD condition. As a result, the fabricated Au/a-Ga₂O₃/Au photodetector shows a fast time response, high responsivity, and excellent wavelength selectivity for solar-blind photodetection. Furthermore, an ultra-thin MgO layer is deposited by PE-ALD to passivate the Au/a-Ga₂O₃/Au interface, resulting in the responsivity of 788 A/W (under 254 nm at 10 V), a 250-nm-to-400-nm rejection ratio of 9.2×103, and the rise time and the decay time of 32 ms and 6 ms, respectively. These results demonstrate that the a-Ga₂O₃ film grown by PE-ALD is a promising candidate for high-performance solar-blind photodetection and potentially can be integrated with Si ICs for commercial production.     

Effect of substrate temperature on the properties of deep ultraviolet transparent conductive ITO/Ga2O3 films

正ITO/Ga_2O_3 bi-layer films were deposited on quartz glass substrates by magnetron sputtering.The effect of substrate temperature on the structure,surface morphology,optical and electrical properties of ITO/Ga_2O_3 films was investigated by an X-ray diffractometer,a scanning electron microscope,a double beam spectrophotometer and the Hall system,respectively.The structural characteristics showed a dependence on substrate temperature. The resistivity of the films varied from 6.71×10~(-3) to 1.91×10~3Ω·cm as the substrate temperature increased from 100 to 350℃.ITO(22 nm)/Ga_2O_3(50 nm) films deposited at 300℃exhibited a low sheet resistance of 373.3Ω/□and high deep ultraviolet transmittance of 78.97%at the wavelength of 300 nm.     

Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RFfrequency range

We have characterized the capacitance and loss tangent for high-k Al₂O₃ and AlTiO_x gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO₂ was demonstrated individually by the proposed Al₂O₃ and AlTiO_x gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO₂ from 100 KHz to 20 GHz. These results suggest that both Al₂O₃ and AlTiO_x are suitable for next generation MOSFET application into RF frequency regime     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.