Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

High-performance Ka-band and V-band HEMTlow-noise amplifiers

Quarter-micron-gate-length high-electron-mobility transistors (HEMTs) have exhibited state-of-the-art low-noise performance at millimeter-wave frequencies, with minimum noise figures of 1.2 dB and 32 GHz and 1.8 dB at 60 GHz. At Ka-band, two-stage and three-stage HEMT low-noise amplifiers have demonstrated noise figures of 1.7 and 1.9 dB, respectively, with associated gains of 17.0 and 24.0 dB at 32 GHz. At V-band, two stage and three-stage HEMT amplifiers yielded noise figures of 3.2 and 3.6 dB, respectively, with associated gains of 12.7 and 20.0 dB and 60 GHz. The 1-dB-gain compression point of all the amplifiers is greater than +6 dBm. The results clearly show the potential of short-gate-length HEMTs for high-performance millimeter-wave receiver application     

High-power V-band pseudomorphic InGaAs HEMT

The author's present the DC and RF power performance of planar-doped channel InGaAs high-electron-mobility transistors (HEMTs). The planar-doped channel (PDC) pseudomorphic GaAs HEMT with 400 μm of gate width exhibited an output power of 184 mW, corresponding to 460 mW/mm, with 4.6-dB saturation gain and 25% power-added efficiency at 55 GHz. Although higher power density is possible, the authors have designed the device to operate at less than 500 mW/mm for thermal and reliability reasons. Devices with unit gate finger widths ranging from 30 to 50 μm were fabricated and characterized, with no performance degradation observed from using the longer gate fingers     

Estimation of fractional changes in peak gNa,g¯Na, ENa, andh∞ (V) of cardiac cells from V˙max of the propagating action potential

Fractional changes in the peak sodium conductances of the cardiac cell membrane during the action potential are often estimated from fractional changes in Vmax. The present model study shows, in reasonable accord with experimental evidence, that this approach is valid for propagating action potentials provided that the membrane capacitance does not change and that the nonsodium current is small at the time of Vmax. When the maximum conductance of the sodium channel (gNa) and the sodium equilibrium potential (ENa) are varied independently of one another, fractional changes in either of them can be predicted from fractional changes in Vmax if a reasonable estimate of the initial value of ENa is available. Manipulations which modify the resting membrane potential without changing gNa allow to calculate fractional changes in the steady-state Na+ inactivation [h infinity (V)] when ENa is known. Simulation runs were carried out for a continuous cable and a discontinuous cable with either a low (1 omega.cm2) or a high (10 omega.cm2) junctional resistance. The predictions of the model are valid in the discontinuous cable provided that the recording point remains strictly the same throughout the series of measurements. Because the high-resistance discontinuous cable provides conditions which reduce further the nonsodium current at the time of Vmax, the accuracy of the predictions are better in this case. It is concluded that properly designed experimental approaches based on Vmax measurements can yield important information on manipulations affecting gNa, ENa, and h infinity (V) during propagation, and that a better accuracy is possible in cardiac muscle when measurements are made during transverse propagation.     

An input-free VT extractor circuit using atwo-transistor differential amplifier

A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V_T is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage     

New techniques for high-frequency RMS-to-DC conversion based on amultifunctional V-to-I convertor

Two bipolar RMS-DC convertor circuits of the computing type which require no rectifier function are discussed. Improved frequency response is thus obtained. RMS-to-DC computation is carried out in the current domain. To make the circuit suitable for voltage driving, a dedicated V-to-I convertor is developed. Measured 1% bandwidths of the RMS-to-DC convertors are 35 and 22 MHz, respectively. Conversion error is less than 1% for the crest factors up to five     

High-power V-band AlInAs/GaInAs on InP HEMTs

The DC and RF performance of δ-doped channel AlInAs/GaInAs on InP power high-electron-mobility transistors (HEMTs) are reported. A 450-μm-wide device with a gate-length of 0.22 μm has achieved an output power of 150 mW (at the 1-dB gain compression point) with power-added efficiency of 20% at 57 GHz. The device has a saturated output power of 200 mW with power-added efficiency of 17%. This is the highest output power measured from a single InP-based HEMT at this frequency, and demonstrates the feasibility of these HEMTs for high-power applications in addition to low-noise applications at V -band     

Electrochemical C-V profiling of heterojunctiondevice structures

Electrochemical capacitance-voltage profiles of multiple (In,Al) GaAs heterostructures have been measured and compared with the results of a numerical calculation of the apparent charge density based on a one-dimensional Poisson solver. The calculation, using layer thicknesses, dopings, and heterojunction band discontinuities obtained from MBE growth calibrations, is in overall agreement with the measured data. The largest discrepancy occurs between the expected and measured heterojunction band discontinuity. This difference is consistent with an electrolyte/semiconductor interface which is not planar on a scale comparable to the layer thickness     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Nonlinear parasitics in MODFETs and MODFET I-Vcharacteristics

A large-signal analysis of the source and drain resistance of MODFETs is reported. Velocity saturation in the two-dimensional electron gas (2DEG) and hypothetical rectifying effects in the n⁺-AlGaAs-i-GaAs interface are accounted for. Rectifying effects are found to be either absent or negligible. Current limitations in the 2DEG lead to the observed compression of the transconductance at large gate voltages, and an improved fit of the MODFET I-V characteristics is demonstrated using an approximate analytic formulation of the current-limited parasitic resistance. The high-frequency dependence of the source and drain resistance is also reported. A decrease of the source impedance for frequencies increasing from 1-30 GHz is predicted and can reach 30%, depending on the device structure. Such a frequency decrease of the parasitics is consistent with the reported increase of the effective transconductance of MODFETs at microwave frequencies. The reported frequency and current-limited parasitic models rely on parameters that can either be measured or calculated and are therefore appropriate for CAD applications     

DC I-V characteristics of field emitter triodes

A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current I_FN. Based on these observations, a simple model has been developed to calculate the I-V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from I_c=I_FN-I_g as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated     

Modeling the gate I/V characteristic of a GaAsMESFET for Volterra-series analysis

The authors show that the Taylor-series coefficients of a FET's gate/drain I/V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I/V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained     

Automatic VT extractors based on ann×n2 MOS transistor array and theirapplication

The development of incremental and decremental V_T extractors based on the square-law characteristic and an n ×n² transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V_T extraction, parameter K of an MOS transistor can also be extracted automatically using the V_T extractor, without any need of calculation and delay, and the extracted V_T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V_T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V_T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented     

Parameter extraction from I-V characteristics ofsingle MOSFETs

A method is presented to extract the bias-dependent series resistances and intrinsic conductance factor of individual MOS transistors from measured I-V characteristics. If applied to groups of scaled channel length devices, it also allows determination of the effective channel length together with the transversal field dependence of the carrier mobility. The method is exactly derived from conventional MOS theory based on the gradual channel approximation, and the deviations from such an ideal case are studied by means of two-dimensional device simulations. Experimental results obtained with n- and p-channel transistors of conventional as well as LDD type are presented to show the correctness of the proposed extraction procedure     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

Near-ideal I-V characteristics of GaInP/GaAsheterojunction bipolar transistors

GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6-μm×6-μm and 100-μm×100-μm devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1×10^-6 A/cm². For the 6-μm×6-μm device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness     

A technique for real-time measurement of Nth-orderderivativesdNV/dIN

A technique for the measurement of device derivatives d ^NV/dI^N of arbitrary order N described. Measurement is accomplished by injecting a test current composed of the sum of N square waves into the rest device, and then multiplying the corresponding voltage change by the product of those same square waves, followed by low-pass filtering. The algorithm is implemented in real time using a mixture of analog and digital circuitry, and its application to semiconductor laser control in high-speed optical communications is described     

High-gain, V-band, low-noise MMIC amplifiers usingpseudomorphic MODFETs

State-of-the-art, 60-GHz, low-noise MMICs based on pseudomorphic modulation-doped FETs, with 0.25-μm×60-μm gates offset 0.3 μm from the source ohmic, are discussed. Single-state low-noise amplifiers (LNAs) exhibited minimum noise figures of 2.90 dB with 4.1 dB of associated gain at 59.25 GHz. Dual-state MMICs had minimum noise figures of 3.5 dB and 10.8 dB of associated gain at 58.50 GHz. Cascaded four-stage LNAs (two dual-stage MMICs) had minimum noise figures of 3.7 dB and over 20.7 dB of associated gain at 58.0 GHz. Finally, when biased for maximum gain, the four-stage amplifier exhibited over 30.4 dB of gain at 60.0 GHz