基于SAT的串扰时延故障测试

随着深亚微米技术的不断发展和芯片运行速率的不断提高,串扰噪声问题越来越严重,对串扰时延测试已成为一个迫切的问题。在组合电路的基础上,将SAT（布尔可满足性）方法引入到串扰引起的时延测试中,通过词法分析和语法分析直接提取Verilog（硬件描述语言）源码的形式模型,组合成CNF（合取范式）形式。并在非鲁棒测试条件下,激活串扰时延故障,约简CNF范式表达式,最终输入SAT求解器得到测试矢量。在标准电路 ISCAS’85上进行实验验证,结果表明：该算法对于串扰时延故障的测试矢量产生是有效的。     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

Rendezvous in networks in spite of delay faults

Two mobile agents, starting from different nodes of an unknown network, have to meet at a node. Agents move in synchronous rounds using a deterministic algorithm. Each agent has a different label, which it can use in the execution of the algorithm, but it does not know the label of the other agent. Agents do not know any bound on the size of the network. In each round an agent decides if it remains idle or if it wants to move to one of the adjacent nodes. Agents are subject to delay faults: if an agent incurs a fault in a given round, it remains in the current node, regardless of its decision. If it planned to move and the fault happened, the agent is aware of it. We consider three scenarios of fault distribution: random (independently in each round and for each agent with constant probability \(0<p<1\)), unbounded adversarial (the adversary can delay an agent for an arbitrary finite number of consecutive rounds) and bounded adversarial (the adversary can delay an agent for at most c consecutive rounds, where c is unknown to the agents). The quality measure of a rendezvous algorithm is its cost, which is the total number of edge traversals. For random faults, we show an algorithm with cost polynomial in the size n of the network and polylogarithmic in the larger label L, which achieves rendezvous with very high probability in arbitrary networks. By contrast, for unbounded adversarial faults we show that rendezvous is not possible, even in the class of rings. Under this scenario we give a rendezvous algorithm with cost \(O(n\ell )\), where \(\ell \) is the smaller label, working in arbitrary trees, and we show that \(\varOmega (\ell )\) is the lower bound on rendezvous cost, even for the two-node tree. For bounded adversarial faults, we give a rendezvous algorithm working for arbitrary networks, with cost polynomial in n, and logarithmic in the bound c and in the larger label L.     

Research and analysis of news transmission path based on microprocessor and image capture

The process of News and analysis theory recipient mind running. However, theoretical research in Finland in recent years provided some new ideas for this process. According to these ideas, all the effects and consequences of media information should be considered the process of knowledge formation when a person obtains information about his world view function, which is by two opposing principles as a guiding rule system dynamic sampling using information previously obtained from a sample selected for each new model. Therefore, the emotional piece has a greater potential fidelity, but at a more complex cost. Current strategies for dynamic non-uniform testing of images depend on examining areas in the most important variants. At the same time, ongoing advances in the hypothesis of the ideal exploration plan provide an ot homogeneous system for excellent testing based on the previous model's use. - Enormous fluffy control applications with virtual frameworks require continuous functionality to fast interface limits; High thickness programmable rationale gadgets, for example, can use the Field Programmable Gate Array (FPGA) to incorporate the most sensible in solitude. Picture transmission device and strategy using the CDMA Correspondence Network have been unveiled. Mechanical assembly to communicate the image captured by the camera.     

一种快速准确控制复杂路径延时的方法

在深亚微米超大规模集成电路的物理设计中,为达到时序收敛经常遇到复杂路径延时的准确控制问题,提出了一种新的准确控制复杂路径延时方法,并使用布局布线工具Synopsys Astro实现。实验结果表明,该方法比传统的ECO（Engineer Change Order）精度高,收敛速度快,可广泛应用于超大规模集成电路物理设计。     

基于MAF模型的串扰时延故障的测试矢量生成

随着深亚微米技术,串扰噪声问题越来越严重。利用MAF模型的基本思想,探讨了一种串扰时延最大化算法,并且利用被修改的FAN算法,生成测试矢量。对于一条敏化通路,利用被修改的FAN算法适当地激活相应的攻击线和受害线,使电路在最恶劣情况下引起最大通路时延,从而实现更有效的时延测试。在标准电路ISCAS’85上进行实验验证,结果表明:该算法对于多攻击线的串扰时延故障的测试矢量产生是有效的。     

延迟容忍网络中路径失效问题的容错研究

延迟容忍网络的路由机制与传统的网络结构有很大不同。针对这类网络中的路径失效问题进行容错研究使得网络在出现路径失效时,能够不影响消息传送,并尽可能地提高消息的成功交付率,从而屏蔽路径失效问题。首先描述了延迟容忍网络中的一种路径失效问题,反映了在路径完全正常、存在部分失效以及完全失效情况下消息交付情况,并针对这一问题研究相应的容错方法。最后给出一个交通延迟容忍网络应用实例,并评价其容错方法的性能。     

Exploiting deterministic TPG for path delay testing

Detection of path delay faults requires two-pattern tests.BIST technique provides a low-cost test solution.This paper proposes an approach to designing a cost-effective deterministic test pattern generator(IPG) for path delay testing.Given a set of pre-generated test-pattern generator(TPG) for path delay testing.Given a set of pre-generated test-pairs with pre-determined fault coverage,a deterministic TPG is synthesized to apply the given test-pair set in a limited test time.To achieve this objective,configuable linear feedback shift register(LFSR)structures are used.Techniques are developed to synthesize such a TPG.which is used to generate an unordered deterministic test-pair set.The resulting TPG is very efficient in terms of hardware size and speed performance.SImulation of academic benchmark circuits has given good results when compared to alternative solutions.     

考虑逻辑门延时的冗余固定故障检测方法

提出利用瞬态电流测试(IDDT Testing)方法检测数字电路中的冗余固定故障。检测时采用双向量模式,充分考虑逻辑门的延时特性。针对两类不同的冗余固定故障,分别给出了激活故障的算法,在此基础上再对故障效应进行传播。SPICE模拟实验结果表明,该方法能有效地区分正常电路与存在冗余故障的电路,可以作为电压测试方法的一种有益的补充。     

Source identification of plant-wide faults based on k nearest neighbor time delay estimation

The identification of plant-wide faults is a very important topic as it enables plant operators to decrease rejections or to increase the product quality. This paper shows a fault propagation approach for this field of interest based on time delay estimation. Due to the fact that the estimation of time delays in multiple-input single-output systems or nonlinear systems is either impossible or very difficult with known methods, a new method based on k nearest neighbor imputation was developed and is validated in this paper theoretically. The effectiveness of the identification algorithm is demonstrated on several simulations and on an industrial hydrocracker plant.     

Designing a microprocessor laboratory

The requirements of a microprocessor teaching and development laboratory are discussed in this paper. Various aspects such as software, printer requirements, file servers and communications networks are discussed as well as the requirement for the microprocessor systems to cater for software and hardware development and for the data-logging type of experiments. A system is proposed that covers most requirements of a teaching and project laboratory for computer or microprocessor courses.     

Architecture of a testable analog fuzzy logic controller

The authors discuss problems of testability of analog fuzzy logic controllers implemented as VLSI chips. Enhancements to standard architecture of fuzzy logic controllers which facilitate testing are proposed. To improve controllability and observability of internal nodes, analog switching blocks are introduced together with some additional circuitry. These blocks allow one to test each basic cell of a fuzzy logic controller (e.g., membership function cell, MINIMAX cell, etc.) separately. The analog switching blocks do not contribute to the power consumption in a working chip end therefore can be used in low-power analog fuzzy logic controllers     

Speed binning with path delay test in 150-nm technology

What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.     

Design considerations for a general-purpose microprocessor

The authors examine the performance, cost, and schedule tradeoffs made for the NS 32532, a 32-bit general-purpose microprocessor. Among its features are a 30-MHz clock frequency, three on-chip caches, a four-stage pipeline, and dedicated mechanisms for multiprocessing support. The authors describe the design constraints set by the VLSI processing and packaging technologies. They address the issue of market requirements by examining the software and hardware considerations for the microprocessor's target applications. After describing the functional partitioning choices, including the means for supporting a memory hierarchy and floating-point operations, they present the NS32532's microarchitecture. They then examine the microprocessor's system interface, the memory reference transactions, and the instruction-flow and data-flow monitoring mechanisms. Finally, the authors present an overview of the methodology adopted to accomplish the design within a strict schedule while achieving full functionality and meeting cost and performance goals     

Machine cycle simulator for a microprocessor

The technique used in the construction of a simulator for a processor affects the range of applications for which the simulator can be used. A machine cycle simulator has been constructed for the MC68000 microprocessor, and some of the advantages of this technique are discussed.     

Spert-II: a vector microprocessor system

The Spert-II fixed point vector microprocessor system performs training and recall faster than commercial workstations for neural networks used in speech recognition research. We have packaged a prototype full custom vector microprocessor, TO, as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system. We originally developed Spert-II to accelerate multiparameter neural network training for speech recognition research. Our speech research algorithms constantly change. Also, neural nets are often integrated with other tasks to form complete applications. We thus desired a general purpose, easily programmable accelerator that could speed up a range of tasks     

Formal verification of a pipelined microprocessor

The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail     

Highly serial architecture for a microprocessor

The paper describes the derivation of an architecture for a microcomputer intended for educational applications. The derivation of the microprogrammable architecture given is followed by one possible instruction set and format of the computer for the user. The microinstructions and their sequence that achieve this view for the user are described in some detail. The architecture is fluid and not only is the microinstruction sequence defined by programmable elements but also a programmable element defines the meanings of the microinstructions and many of the interconnections within the processor. Wherever possible steps have been taken to minimize chip area usually by sacrificing parallel for serial operation.