Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

Rendezvous in networks in spite of delay faults

Two mobile agents, starting from different nodes of an unknown network, have to meet at a node. Agents move in synchronous rounds using a deterministic algorithm. Each agent has a different label, which it can use in the execution of the algorithm, but it does not know the label of the other agent. Agents do not know any bound on the size of the network. In each round an agent decides if it remains idle or if it wants to move to one of the adjacent nodes. Agents are subject to delay faults: if an agent incurs a fault in a given round, it remains in the current node, regardless of its decision. If it planned to move and the fault happened, the agent is aware of it. We consider three scenarios of fault distribution: random (independently in each round and for each agent with constant probability \(0<p<1\)), unbounded adversarial (the adversary can delay an agent for an arbitrary finite number of consecutive rounds) and bounded adversarial (the adversary can delay an agent for at most c consecutive rounds, where c is unknown to the agents). The quality measure of a rendezvous algorithm is its cost, which is the total number of edge traversals. For random faults, we show an algorithm with cost polynomial in the size n of the network and polylogarithmic in the larger label L, which achieves rendezvous with very high probability in arbitrary networks. By contrast, for unbounded adversarial faults we show that rendezvous is not possible, even in the class of rings. Under this scenario we give a rendezvous algorithm with cost \(O(n\ell )\), where \(\ell \) is the smaller label, working in arbitrary trees, and we show that \(\varOmega (\ell )\) is the lower bound on rendezvous cost, even for the two-node tree. For bounded adversarial faults, we give a rendezvous algorithm working for arbitrary networks, with cost polynomial in n, and logarithmic in the bound c and in the larger label L.     

Source identification of plant-wide faults based on k nearest neighbor time delay estimation

The identification of plant-wide faults is a very important topic as it enables plant operators to decrease rejections or to increase the product quality. This paper shows a fault propagation approach for this field of interest based on time delay estimation. Due to the fact that the estimation of time delays in multiple-input single-output systems or nonlinear systems is either impossible or very difficult with known methods, a new method based on k nearest neighbor imputation was developed and is validated in this paper theoretically. The effectiveness of the identification algorithm is demonstrated on several simulations and on an industrial hydrocracker plant.     

Designing a microprocessor laboratory

The requirements of a microprocessor teaching and development laboratory are discussed in this paper. Various aspects such as software, printer requirements, file servers and communications networks are discussed as well as the requirement for the microprocessor systems to cater for software and hardware development and for the data-logging type of experiments. A system is proposed that covers most requirements of a teaching and project laboratory for computer or microprocessor courses.     

Architecture of a testable analog fuzzy logic controller

The authors discuss problems of testability of analog fuzzy logic controllers implemented as VLSI chips. Enhancements to standard architecture of fuzzy logic controllers which facilitate testing are proposed. To improve controllability and observability of internal nodes, analog switching blocks are introduced together with some additional circuitry. These blocks allow one to test each basic cell of a fuzzy logic controller (e.g., membership function cell, MINIMAX cell, etc.) separately. The analog switching blocks do not contribute to the power consumption in a working chip end therefore can be used in low-power analog fuzzy logic controllers     

Speed binning with path delay test in 150-nm technology

What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.     

Formal verification of a pipelined microprocessor

The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail     

Highly serial architecture for a microprocessor

The paper describes the derivation of an architecture for a microcomputer intended for educational applications. The derivation of the microprogrammable architecture given is followed by one possible instruction set and format of the computer for the user. The microinstructions and their sequence that achieve this view for the user are described in some detail. The architecture is fluid and not only is the microinstruction sequence defined by programmable elements but also a programmable element defines the meanings of the microinstructions and many of the interconnections within the processor. Wherever possible steps have been taken to minimize chip area usually by sacrificing parallel for serial operation.     

Design considerations for a general-purpose microprocessor

The authors examine the performance, cost, and schedule tradeoffs made for the NS 32532, a 32-bit general-purpose microprocessor. Among its features are a 30-MHz clock frequency, three on-chip caches, a four-stage pipeline, and dedicated mechanisms for multiprocessing support. The authors describe the design constraints set by the VLSI processing and packaging technologies. They address the issue of market requirements by examining the software and hardware considerations for the microprocessor's target applications. After describing the functional partitioning choices, including the means for supporting a memory hierarchy and floating-point operations, they present the NS32532's microarchitecture. They then examine the microprocessor's system interface, the memory reference transactions, and the instruction-flow and data-flow monitoring mechanisms. Finally, the authors present an overview of the methodology adopted to accomplish the design within a strict schedule while achieving full functionality and meeting cost and performance goals     

Machine cycle simulator for a microprocessor

The technique used in the construction of a simulator for a processor affects the range of applications for which the simulator can be used. A machine cycle simulator has been constructed for the MC68000 microprocessor, and some of the advantages of this technique are discussed.     

Spert-II: a vector microprocessor system

The Spert-II fixed point vector microprocessor system performs training and recall faster than commercial workstations for neural networks used in speech recognition research. We have packaged a prototype full custom vector microprocessor, TO, as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system. We originally developed Spert-II to accelerate multiparameter neural network training for speech recognition research. Our speech research algorithms constantly change. Also, neural nets are often integrated with other tasks to form complete applications. We thus desired a general purpose, easily programmable accelerator that could speed up a range of tasks     

DISCUS — a distributed control microprocessor system

DISCUS (distributed control microprocessor system) represents a simple, yet effective approach to multimicroprocessor applications. It is being developed and used at RSRE. The basic concept is of a collection of asynchronous microprocessors cooperating to perform a task, with each processor dedicated to one function, and one function only. Interprocess communication is achieved through an operating system resident in each processor, via a specified hardware and software interface. It is also possible to add, online, an extra processor, containing identical software to a similar processor already in the system, thus increasing the functions throughput by parallel working. The prototype system consists of Intel 8080 processors, and programs are written in CORAL.An experimental digital communications switch is being built in conjunction with other work at RSRE as the first application of DISCUS and its concepts.     

Alternative approach to a microprocessor teaching laboratory

A recent paper discussed the way in which microprocessors are being used for teaching computer science at Strathclyde University. This article discusses an alternative system being implemented at Rhodes University. The chief difference between the two is the attitude towards breakdowns.     

Test development for a third-version ColdFire microprocessor

The design-for-test methodology of the MCF5307 device is described, illustrating issues faced, how solutions were derived, and results     

TITAC: design of a quasi-delay-insensitive microprocessor

TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation     

基于微机装置的改进型前加速保护方案

重合闸前加速保护方式在配电网中被广泛应用.它节省投资,接线简单,可以快速切除瞬时性故障,但是当重合于永久性故障时,保护的动作时间可能较长,这对于负荷供电和系统安全都是极为不利的.为此,本文提出了一种适用于微机装置的改进型保护方案,它利用微机保护强大的记忆和逻辑功能,当发生重合于永久性故障时,该方案能够自动识别并立刻投入快速保护,从而大大缩短了对于永久性故障的切除时间.该方案原理简单,容易实现,不需额外增加任何设备,因而功能可靠,便于实际应用.     

Design of the structure of a high-efficiency microcomputer on microprocessor sets

Conclusions The proposed approach to design of high-efficiency microcomputers is based on optimum data distribution among the modules of the modular set of the microprocessor hardware, which allows to take into account the new capabilities in organizing the microcomputer structure afforded by the widespread introduction of large integration circuits. The principles of optimum data distribution formulated in the paper can be used to develop a method for the design of high-efficiency microcomputers.Translated from Kibernetika, No. 2, pp. 43–47, March–April, 1983.