A Novel Discrete Dimming Ballast for Linear Fluorescent Lamps

A novel discrete dimming ballast for linear fluorescent lamps is proposed in this paper. A proposed dimming control circuit is combined with a ballast module for multiple lamps to realize control of three discrete lighting levels. Compared with conventional step dimming or on– off control methods, the proposed discrete dimming method has the following advantages: 1) digital signal is generated by the dimming control circuit to control the lamps' turn- on and -off, which makes the system more reliable and integrated; 2) the proposed discrete dimming system replaces relays, which are necessary in conventional lamp on–off control, and therefore decreases the system cost; 3) the proposed dimming ballast can be installed by keeping the original wiring system. This makes the upgrading of a lighting system more effective and efficient; 4) the dimming control circuit also provides a good isolation for operating the low-voltage wall switches by hand safely. Both theoretical, simulation, and experimental results are in good agreement.      

High-Performance Low-Power Selective Precharge Schemes for Address Decoders

Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the and–nor and sense amplifier (Sense-Amp) decoders, are compared to the nor decoder using 90-nm CMOS technology. The Sense-Amp decoder dissipates between 29.5% and 50.1% and the and–nor decoder dissipates between 73.7% and 104.4% of the energy dissipated by the nor decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the and–nor decoder is 80.8% of the nor decoder delay.      

Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

The impact of scaling the depth of the shallow trench isolation (STI) region, underneath the gate-to-drain overlap, on the STI drain-extended metal–oxide–semiconductor (DeMOS) mixed-signal performance and hot-carrier behavior is systematically investigated in this work. For the first time, we discuss a dual-STI process for input/output applications. Furthermore, the differences in the hot-carrier behavior of various drain-extended devices are studied under the on- and off-states. We found that the non-STI DeMOS devices are quite prone to failure when compared with the STI DeMOS devices in both the on- and off- states. We introduced a more accurate way of predicting hot-carrier degradation in these types of devices in the on-state. We show that scaling the depth of the STI underneath the gate is the key for improving both the mixed-signal and hot-carrier reliability performances of these devices.      

Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of nand and nor circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of nand and nor are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.      

Normally On/Off Integrated Latching Acceleration Switch With Controlled Fracture Beams and Independent Multicontact

This letter reports an acceleration latching switch with integrated normally on/off paths. The normally on path, formed by notched beams connected in series, will be broken and latched to reach the open state when the acceleration exceeds the threshold. A multicontact is adopted for the normally off path, while both paths are mechanically separated from the proof mass to prevent them from the impact of the proof mass at the latched state. Experimental results show that the latching shock is 10 000 G, and the response time is about 0.1 ms. The normally on path has an on-state resistance of 4.0 $Omega$ and an allowable current of 200 mA, whereas the normally off path has an on-state resistance of 3.8 $Omega$ and a maximum current of 140 mA.      

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.      

Logic Operation of HTS SFQ Logic Family

A high-$T_{c}$ superconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve $I_{c}$ uniformity. As a result, all circuits were successfully tested and show at least $pm$40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using $hbox{YBa}_{2} hbox{Cu}_{3}hbox{O}_{7 - delta}$ ramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.      

nand Flash Memory and Its Role in Storage Architectures

This papers reviews the increasing role of nand flash memory in storage architectures. nand flash has enjoyed a phenomenal growth rate in storage capacities as well as a steady decline in pricing during the past few years. These developments have enabled nand to enter and possibly change or displace some traditional storage architectures. However, besides cost, nand flash memory has some reliability and performance issues that will slow its adoption into all storage architectures. This paper will analyze the advantages and disadvantages of this technology and the implications to the current and possible future storage architectures. Moreover, we will analyze nand flash future density and costs trends and compare them with the traditional hard disk drive.      

Optical Encryption With OCDMA Code Swapping Using All-Optical xor Logic Gate

A novel optical code-division multiple access (OCDMA) transmission system with all-optical exclusive or (xor) encryption architecture is proposed and demonstrated. This all-optical system conducts OCDMA code swapping based on xor operation. This multilayer approach eliminates radio-frequency data radiation and improves the confidentiality of the transmission system.      

The $hbox{1}/f$ Noise and Random Telegraph Noise Characteristics in Floating-Gate nand Flash Memories

We have characterized low-frequency noise (LFN) such as $hbox{1}/f$ noise and random telegraph noise (RTN) in a nand Flash memory cell string for the first time and shown its fundamental properties. The nand Flash memory cells showed specific LFN characteristics under various conditions such as bit-line bias, word-line bias of a selected cell, and pass bias of the unselected cells in the nand string. Also, LFN was investigated with the program/erase (P/E) cycling of a cell or all cells in a string, and maximum threshold voltage fluctuation of several tens of millivolts after $sim$100 000 cycles at the 70-nm technology node was shown. Finally, we predicted the effects of LFN in sub-70-nm nand Flash memories.      

Timing Jitter Reduction by All-Optical Signal Regeneration Using a Polarization Bistable VCSEL

All-optical signal regeneration is experimentally demonstrated using a polarization bistable vertical-cavity surface-emitting laser. The retiming operation of signal regeneration is performed by using an AND gate operation and a reset operation. An optical clock pulse and input data signal are used for the AND gate operation. The timing jitter of the regenerated signal is reduced by optimizing the injection power ratio of the clock pulse and the data signal. The retiming operation is analyzed using a simple model that includes random fluctuation of the polarization switching threshold and bandwidth limitation of the response to the injection light.      

XPM Response of a Chirped DFB-SOA All-Optical Flip-Flop Injected With an Assist Light at Transparency

In this paper, based on the coupled-mode and carrier rate equations, we have derived a dynamic model for a linearly chirped distributed feedback semiconductor optical amplifier (DFB-SOA) all-optical flip-flop (DFB-SOA-FF) and analyzed it numerically. We have investigated the effects of assist light and cross-phase modulation (XPM) on the dynamic response and rise and fall times of the DFB-SOA-FF, for the first time. We have also shown that injection of an assist light, within the transparency spectrum, into a DFB-SOA with a linearly chirped grating can improve the device speed limitation, significantly. Values of the ON and OFF switching times for such an optical flip-flop, in an optimized condition, are found to be 190 and 195 ps, respectively. These show reductions of more than three times in the ON and seven times in the OFF switching times with respect to those of the uniform grating DFB-SOA-FF. Finite-difference time-domain method is used for numerical simulations.      

Demonstration of an All-Optical OCDMA Encryption and Decryption System With Variable Two-Code Keying

We demonstrate the first all-optical optical code-division multiple-access (OCDMA) encryption and decryption system with variable two-code keying. The nonlinear optical loop mirror (NOLM)-based exclusive or (xor) employed in encryption utilizes the shortest length silica-based nonlinear fiber element to date, enabling a compact architecture. Fiber Bragg grating arrays create wavelength-hopping time-spreading OCDMA codes from broadband pulses at output ports of the xor resulting in variable two-code keying, a code-switching modulation format characterized by a random alternation in bit representation and immunity to differential analysis unlike fixed two-code keying. The terahertz optical asymmetric demultiplexer employed in decryption shows mutual compatibility of nonlinear fiber-based and semiconductor optical amplifier-based NOLM configurations. Our architecture can potentially perform one-time pad encryption and decryption for unconditional security.      

A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose–Chaudhuri–Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) nor flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time–area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.      

A Self-Disabled Sensing Technique for Content-Addressable Memories

A low-power content-addressable memory (CAM) using a differential match line (ML) sense amplifier is proposed in this work. The proposed self-disabled sensing technique can choke the charge current fed into the ML right after the matching comparison is generated. Instead of using typical nor/ nand-type CAM cells with the single-ended ML, the proposed novel nand CAM cell with the differential ML design can boost the speed of comparison without sacrificing power consumption. In addition, the 9-T CAM cell with disabled read-out circuit provides the complete write, read, and comparison functions to refresh the data and verify its correctness before searching. The CAM with the proposed technique is implemented on silicon to justify the performance by using a standard 0.13-$muhbox{m}$ complementary metal–oxide–semiconductor process. The energy consumption of the searching process is 1.872 fJ/bit/search.      

SOA-Based Ultrafast Multifunctional All-Optical Logic Gates With PolSK Modulated Signals

In this paper, we propose a novel scheme for ultrafast multifunctional all-optical logic gates, which can achieve not only simple logic gates including AND, NOR, $ {S_{1}}{bar S_{2}} $, $ {bar S_{1}}{S_{2}} $, XNOR, and XOR but also complex logic gates including half adder, half subtracter, decoder, and comparer based on four-wave mixing in semiconductor optical amplifiers (SOAs) with polarization-shift-keying (PolSK) modulated signals. A comprehensive polarization-dependent broadband dynamic model of this kind of ultrafast multifunctional all-optical logic gates is presented. By numerical simulation, the multifunctional all-optical logic gates are theoretically realized at 40 Gbit/s. The effects of two input signal powers, injected current, frequency detuning, and polarization dependence of SOA on the output performance of the multifunctional all-optical logic gates are theoretically investigated in detail. The results indicate that this scheme is free of pattern effect due to using the PolSK modulation format. Moreover, the nice eye opening of the logic gates indicates the good performance of the proposed ultrafast multifunctional all-optical logic gates. This scheme is potential for applications in future high bit rate optical networks.      

160 Gb/s Time-Domain Channel Extraction/Insertion and All-Optical Logic Operations Exploiting a Single PPLN Waveguide

160 Gb/s all-optical signal processing is demonstrated exploiting pump depletion in addition to sum and difference frequency generation (SFG/DFG) in a single periodically poled lithium-niobate (PPLN) waveguide. 160 Gb/s time-domain extraction and insertion operations of channels are obtained in an optical time division multiplexing (OTDM) system. Moreover, 160 Gb/s digital operations including half-adder, half-subtracter and and/or/xor functions are carried out. The use of pump depletion effect allows to process ultrafast signals due to its high efficiency and ultrafast dynamics. 160 Gb/s bit error rate (BER) measurements confirm the effectiveness of all presented functionalities.      

Buffered Cross-Bar Switches, Revisited: Design Steps, Proofs and Simulations Towards Optimal Rate and Minimum Buffer Memory

Regarding the packet-switching problem, we prove that the weighed max-min fair service rates comprise the unique Nash equilibrium point of a strategic game, specifically a throughput auction based on a “least-demanding first-served” principle. We prove that a buffered crossbar switch can converge to this equilibrium with no pre-computation or internal acceleration, with either randomized or deterministic schedulers, (the latter with a minimum buffering of a single-packet per crosspoint). Finally, we present various simulation results that corroborate and extend our analysis.      

ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

We demonstrate ACCNT (pronounced as “accent”), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high on– off ratios $(hbox{10}^{4}{-} hbox{10}^{6})$ while preserving the current drive. In addition, this metallic-nanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSI-compatible metallic-nanotube-tolerant design methodology.      

Switching Time in Relaxation Oscillations of Emitter-Coupled Multivibrators

This paper gives an estimation of the switching time between on and off transistor states for the emitter-coupled multivibrator. The calculation uses the root locus of the characteristic equation for the oscillator small-signal equivalent circuit, while changing the device current as a parameter. The switching time is found using a fitting location of the root in the right half of the $s$-plane. The oscillation frequency is also obtained. The approach provides a further insight into switching behavior of relaxation oscillators, gives an accurate estimation of the oscillation frequency, and allows one to establish a useful connection between sinusoidal and relaxation oscillators. The theoretical results are confirmed by simulations.