Aligning Solution‐Derived Carbon Nanotube Film with Full Surface Coverage for High‐Performance Electronics Applications

The main challenge for application of solution‐derived carbon nanotubes (CNTs) in high performance field‐effect transistor (FET) is how to align CNTs into an array with high density and full surface coverage. A directional shrinking transfer method is developed to realize high density aligned array based on randomly orientated CNT network film. Through transferring a solution‐derived CNT network film onto a stretched retractable film followed by a shrinking process, alignment degree and density of CNT film increase with the shrinking multiple. The quadruply shrunk CNT films present well alignment, which is identified by the polarized Raman spectroscopy and electrical transport measurements. Based on the high quality and high density aligned CNT array, the fabricated FETs with channel length of 300 nm present ultrahigh performance including on‐state current I_on of 290 µA µm^?1 (V_ds = ?1.5 V and V_gs = ?2 V) and peak transconductance g_m of 150 µS µm^?1, which are, respectively, among the highest corresponding values in the reported CNT array FETs. High quality and high semiconducting purity CNT arrays with high density and full coverage obtained through this method promote the development of high performance CNT‐based electronics.     

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor(CNT FET)has been considered as a promising candidate for future high-performance and low-power integrated circuits(ICs)applications owing to its ballistic transport and excellent immunity to short channel effects(SCEs).Still,it easily suffers from the ambipolar property,and severe leakage current at off-state originated from gate-induced drain leakage(GIDL)in CNT FETs with small bandgap.Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs,there is still a lack of the structure with excellent scalability,which will hamper the development of CNT FETs toward a competitive technology node.Here,we explore how the device geometry design affects the leakage current in CNT FETs,and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional(2D)TCAD simulations.Among all the proposed structures,the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process.According to the simulation results,the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/μm and an on-current as high as about 2.1 mA/μm at a supply voltage of-1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.     

A Fermi‐Level‐Pinning‐Free 1D Electrical Contact at the Intrinsic 2D MoS2–Metal Junction

Currently 2D crystals are being studied intensively for use in future nanoelectronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier‐free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky–Mott rule and resulting in significant suppression of carrier transport in the device. Here, MoS₂ polarity control is realized without extrinsic doping by employing a 1D elemental metal contact scheme. The use of high‐work‐function palladium (Pd) or gold (Au) enables a high‐quality p‐type dominant contact to intrinsic MoS₂, realizing Fermi level depinning. Field‐effect transistors (FETs) with Pd edge contact and Au edge contact show high performance with the highest hole mobility reaching 330 and 432 cm² V^?1 s^?1 at 300 K, respectively. The ideal Fermi level alignment allows creation of p‐ and n‐type FETs on the same intrinsic MoS₂ flake using Pd and low‐work‐function molybdenum (Mo) contacts, respectively. This device acts as an efficient inverter, a basic building block for semiconductor integrated circuits, with gain reaching 15 at V_D = 5 V.     

High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications

WSe₂ is thought to be one of the best emerging p-type transition metal dichalcogenide (TMD) materials for potential low-power complementary metal oxide semiconductor (CMOS) circuit applications. However, the contact barrier and the interface quality hinder the performance of p-type field effect transistors (FETs) with WSe₂ films. In this work, metals with different work functions—Pd, Pt, and Ag—were systematically investigated as contacts for WSe₂ to decrease the contact resistances at source/drain electrodes and potentially improve transistor performance. Optimized p-type multilayer WSe₂ FETs with Pd contacts were successfully fabricated, and excellent electrical characteristics were obtained: a hole mobility of 36 cm²V^?1 s^?1; a high on/off ratio, over 10⁶; and a record low sub-threshold swing, SS?=?95 mV/dec, which may be attributed to the small Schottky barrier height of 295 meV between Pd and WSe₂, and strong Fermi-level pinning near the top of the valence band at the interface. Finally, a full-functional CMOS inverter was also demonstrated, consisting of a p-type WSe₂ FET together with a normal n-type MoS₂ FET. This confirmed the potential of TMD FETs in future low-power CMOS digital circuit applications.

     

Ultrahigh Responsivity in Graphene–ZnO Nanorod Hybrid UV Photodetector

Ultraviolet (UV) photodetectors based on ZnO nanostructure/graphene (Gr) hybrid‐channel field‐effect transistors (FETs) are investigated under illumination at various incident photon intensities and wavelengths. The time‐dependent behaviors of hybrid‐channel FETs reveal a high sensitivity and selectivity toward the near‐UV region at the wavelength of 365 nm. The devices can operate at low voltage and show excellent selectivity, high responsivity (R_I ), and high photoconductive gain (G). The change in the transfer characteristics of hybrid‐channel FETs under UV light illumination allows to detect both photovoltage and photocurrent. The shift of the Dirac point (V _Dirac) observed during UV exposure leads to a clearer explanation of the response mechanism and carrier transport properties of Gr, and this phenomenon permits the calculation of electron concentration per UV power density transferred from ZnO nanorods and ZnO nanoparticles to Gr, which is 9 × 10¹⁰ and 4 × 10¹⁰ per mW, respectively. The maximum values of R_I and G infer from the fitted curves of R_I and G versus UV intensity are 3 × 10⁵ A W^?1 and 10⁶, respectively. Therefore, the hybrid‐channel FETs studied herein can be used as UV sensing devices with high performance and low power consumption, opening up new opportunities for future optoelectronic devices.     

Direct Observation of Contact Reaction Induced Ion Migration and its Effect on Non-Ideal Charge Transport in Lead Triiodide Perovskite Field-Effect Transistors

The migration of ionic defects and electrochemical reactions with metal electrodes remains one of the most important research challenges for organometal halide perovskite optoelectronic devices. There is still a lack of understanding of how the formation of mobile ionic defects impact charge carrier transport and operational device stability, particularly in perovskite field-effect transistors (FETs), which tend to exhibit anomalous device characteristics. Here, the evolution of the n-type FET characteristics of one of the most widely studied materials, Cs_0.05FA_0.17MA_0.78PbI_3, is investigated during repeated measurement cycles as a function of different metal source–drain contacts and precursor stoichiometry. The channel current increases for high work function metals and decreases for low work function metals when multiple cycles of transfer characteristics are measured. The cycling behavior is also sensitive to the precursor stoichiometry. These metal/stoichiometry-dependent device non-idealities are correlated with the quenching of photoluminescence near the positively biased electrode. Based on elemental analysis using electron microscopy the observations can be understood by an n-type doping effect of metallic ions that are created by an electrochemical interaction at the metal–semiconductor interface and migrate into the channel. The findings improve the understanding of ion migration, contact reactions, and the origin of non-idealities in lead triiodide perovskite FETs.     

An Ambipolar Superconducting Field‐Effect Transistor Operating above Liquid Helium Temperature

Superconducting (SC) devices are attracting renewed attention as the demands for quantum‐information processing, meteorology, and sensing become advanced. The SC field‐effect transistor (FET) is one of the elements that can control the SC state, but its variety is still limited. Superconductors at the strong‐coupling limit tend to require a higher carrier density when the critical temperature (T_C) becomes higher. Therefore, field‐effect control of superconductivity by a solid gate dielectric has been limited only to low temperatures. However, recent efforts have resulted in achieving n‐type and p‐type SC FETs based on organic superconductors whose T_C exceed liquid He temperature (4.2 K). Here, a novel “ambipolar” SC FET operating at normally OFF mode with T_C of around 6 K is reported. Although this is the second example of an SC FET with such an operation mode, the operation temperature exceeds that of the first example, or magic‐angle twisted‐bilayer graphene that operates at around 1 K. Because the superconductivity in this SC FET is of unconventional type, the performance of the present device will contribute not only to fabricating SC circuits, but also to elucidating phase transitions of strongly correlated electron systems.     

Fabrication of nanometer-scale carbon nanotube field-effect transistors on flexible and transparent substrate

We have successfully fabricated nanometer-scale carbon nanotube field effect transistors (CNT FETs) on a flexible and transparent substrate by electron-beam lithography. The measured current-voltage data show good hole conduction FET characteristics, and the on/off ratio of the current is more than 10(2). The conductance (as well as current) systematically decreases with the increase of the strain, suggesting that the bending of the substrate still affects the deformation condition of the short channel CNT FETs.     

Reliability tests and improvements for Sc-contacted n-type carbon nanotube transistors

Scandium (Sc) contacted n-type carbon nanotube (CNT) field-effected transistors (FETs) with back and top-gate structure have been fabricated, and their stability in air were investigated. It was shown that oxygen and water molecules may affect both the nanotube channel and Sc/nanotube contacts, leading to deteriorated contact quality and device performance. These negative effects associated with the instability of n-type carbon nanotube FETs can be eliminated through passivating the CNT devices by a thin layer of atomic-layer-deposition grown Al₂O₃ insulator. After passivation, the n-type carbon nanotube FETs are shown to exhibit excellent atmosphere stability even after being tested and exposed to air for over 146 days, and then much smoother output characteristics and reduced gate voltage hysteresis from 1 to 0.1 V were demonstrated when compared with devices without passivation. Lasting power-on tests were also performed on the passivated CNT FETs under large gate stress and high drain current in air for at least 10 h, revealing null device degradation and sometimes even improved performance. These results promise that passivated CNT devices are reliable in air and may be used in practical applications.      

Photo‐/Thermal‐Responsive Field‐Effect Transistor upon Blending Polymeric Semiconductor with Hexaarylbiimidazole toward Photonically Programmable and Thermally Erasable Memory Device

It is shown that the semiconducting performance of field‐effect transistors (FETs) with PDPP4T (poly(diketopyrrolopyrrole‐quaterthiophene)) can be reversibly tuned by UV light irradiation and thermal heating after blending with the photochromic hexaarylbiimidazole compound (p‐NO₂‐HABI). A photo‐/thermal‐responsive FET with a blend thin film of PDPP4T and p‐NO₂‐HABI is successfully fabricated. The transfer characteristics are altered significantly with current enhanced up to 10⁶‐fold at V_G = 0 V after UV light irradiation. However, further heating results in the recovery of the transfer curve. This approach can be extended to other semiconducting polymers such as P3HT (poly(3‐hexyl thiophene)), PBTTT (poly(2,5‐bis(3‐tetradecylthiophen‐2‐yl)thieno[3,2‐b] thiophene)) and PDPPDTT (poly(diketopyrrolopyrrole‐dithienothiophene)). It is hypothesized that TPIRs (2,4,5‐triphenylimidazolyl radicals) formed from p‐NO₂‐HABI after UV light irradiation can interact with charge defects at the gate dielectric–semiconductor interface and those in the semiconducting layer to induce more hole carriers in the semiconducting channel. The application of the blend thin film of PDPP4T and p‐NO₂‐HABI is further demonstrated to fabricate the photonically programmable and thermally erasable FET‐based nonvolatile memory devices that are advantageous in terms of i) high ON/OFF current ratio, ii) nondestructive reading at low electrical bias, and iii) reasonably highly stable ON‐state and OFF‐state.     

Effects of Water and Different Solutes on Carbon‐Nanotube Low‐Voltage Field‐Effect Transistors

Semiconducting single‐walled carbon nanotubes (swCNTs) are a promising class of materials for emerging applications. In particular, they are demonstrated to possess excellent biosensing capabilities, and are poised to address existing challenges in sensor reliability, sensitivity, and selectivity. This work focuses on swCNT field‐effect transistors (FETs) employing rubbery double‐layer capacitive dielectric poly(vinylidene fluoride‐co‐hexafluoropropylene). These devices exhibit small device‐to‐device variation as well as high current output at low voltages (<0.5 V), making them compatible with most physiological liquids. Using this platform, the swCNT devices are directly exposed to aqueous solutions containing different solutes to characterize their effects on FET current–voltage (FET I–V) characteristics. Clear deviation from ideal characteristics is observed when swCNTs are directly contacted by water. Such changes are attributed to strong interactions between water molecules and sp²‐hybridized carbon structures. Selective response to Hg²⁺ is discussed along with reversible pH effect using two distinct device geometries. Additionally, the influence of aqueous ammonium/ammonia in direct contact with the swCNTs is investigated. Understanding the FET I–V characteristics of low‐voltage swCNT FETs may provide insights for future development of stable, reliable, and selective biosensor systems.     

Threshold Voltage Control of Multilayered MoS2 Field‐Effect Transistors via Octadecyltrichlorosilane and their Applications to Active Matrixed Quantum Dot Displays Driven by Enhancement‐Mode Logic Gates

In recent past, for next‐generation device opportunities such as sub‐10 nm channel field‐effect transistors (FETs), tunneling FETs, and high‐end display backplanes, tremendous research on multilayered molybdenum disulfide (MoS₂) among transition metal dichalcogenides has been actively performed. However, nonavailability on a matured threshold voltage control scheme, like a substitutional doping in Si technology, has been plagued for the prosperity of 2D materials in electronics. Herein, an adjustment scheme for threshold voltage of MoS₂ FETs by using self‐assembled monolayer treatment via octadecyltrichlorosilane is proposed and demonstrated to show MoS₂ FETs in an enhancement mode with preservation of electrical parameters such as field‐effect mobility, subthreshold swing, and current on–off ratio. Furthermore, the mechanisms for threshold voltage adjustment are systematically studied by using atomic force microscopy, Raman, temperature‐dependent electrical characterization, etc. For validation of effects of threshold voltage engineering on MoS₂ FETs, full swing inverters, comprising enhancement mode drivers and depletion mode loads are perfectly demonstrated with a maximum gain of 18.2 and a noise margin of ≈45% of 1/2 V_DD. More impressively, quantum dot light‐emitting diodes, driven by enhancement mode MoS₂ FETs, stably demonstrate 120 cd m^?2 at the gate‐to‐source voltage of 5 V, exhibiting promising opportunities for future display application.     

Electric Field Effect on the Magnetic Properties of III–V Ferromagnetic Semiconductor (In,Mn)As and ((Al),Ga,Mn)As

We have investigated the magnetotransport properties of field-effect transistors (FET) having a III–V ferromagnetic semiconductor channel layer. One can control not only the ferromagnetic transition temperature T _C but also the magnetization and the coercive force of (In,Mn)As channel layers isothermally and reversibly by gate electric fields. A small change of the magnetization upon application of gate electric fields is also observed in FETs with a (Ga,Mn)As channel. Results on a (Al,Ga,Mn)As channel FET are also presented.     

Quantitative Experimental Analysis of Schottky Barriers and Poole–Frenkel Emission in Carbon Nanotube Devices

In this paper, we investigated carbon nanotube FETs (CNT FETs) utilizing semiconducting single-walled CNTs (SWCNTs). Multiple devices, each of different metal source and drain contacts, were fabricated on a single SWCNT. Over specific temperature regimes, transport properties of the devices were found to be consistent with the Bethe theory of thermionic emission for Schottky contacts, and the Poole–Frenkel emission was dependent on the device position. As was expected, transport from thermionic emission over the barrier was found to be the dominant mechanism. Barriers of 25–41 meV were present, as found by activation energy analysis for temperatures ranging from 20 to 300 K for the devices. A Schottky diode was also fabricated on a separate nanotube using an ohmic contact at the Pd source and a Schottky contact for the Ag drain electrode. Assuming the same physical assumptions for an Si semiconductor device, the results indicate an ideality factor greater than 2, Schottky barrier of $sim$0.37 eV, and image charge lowering of $sim$0.1 eV.      

High-performance carbon nanotube light-emitting diodes with asymmetric contacts

Electroluminescence (EL) measurements are carried out on a two-terminal carbon nanotube (CNT) based light-emitting diode (LED). This two-terminal device is composed of an asymmetrically contacted semiconducting single-walled carbon nanotube (SWCNT). On the one end the SWCNT is contacted with Sc and on the other end with Pd. At large forward bias, with the Sc contact being grounded, electrons can be injected barrier-free into the conduction band of the SWCNT from the Sc contact and holes be injected into the valence band from the Pd electrode. The injected electrons and holes recombine radiatively in the SWCNT channel yielding a narrowly peaked emission peak with a full width at half-maximum of about 30 meV. Detailed EL spectroscopy measurements show that the emission is excitons dominated process, showing little overlap with that associated with the continuum states. The performance of the LED is compared with that based on a three-terminal field-effect transistor (FET) that is fabricated on the same SWCNT. The conversion efficiency of the two-terminal diode is shown to be more than three times higher than that of the FET based device, and the emission peak of the LED is much narrower and operation voltage is lower.     

Fabrication and characterization of nano-channel field effect transistors patterned by AFM anodic oxidation

We report a top-down approach based on atomic force microscope (AFM) local anodic oxidation (LAO) for the fabrications of the nanowire and nano-ribbon field effect transistors (FETs). In order to investigate the transport characteristics of nano-channel, we fabricated simple FET structures with channel width W approximately 300 nm (nanowire) and 10 microm (nano-ribbon) on 20 nm-thick silicon-on-insulator (SOL) wafers. In order to investigate the transport behavior in the device with different channel geometries, we have performed detailed two-dimensional simulations of nanowire and reference nano-ribbon FETs with a fixed channel length L and thickness t but varying channel width W from 300 nm to 10 microm. By evaluating the charge distributions, we have shown that the increase of 'on state' conduction current in SiNW channel is a dominant factor, which consequently result in the improved on/off current ratio of the nanowire FET.     

Multifunctional van der Waals Broken‐Gap Heterojunction

The finite energy band‐offset that appears between band structures of employed materials in a broken‐gap heterojunction exhibits several interesting phenomena. Here, by employing a black phosphorus (BP)/rhenium disulfide (ReS₂) heterojunction, the tunability of the BP work function (Φ _BP) with variation in flake thickness is exploited in order to demonstrate that a BP‐based broken‐gap heterojunction can manifest diverse current‐transport characteristics such as gate tunable rectifying p–n junction diodes, Esaki diodes, backward‐rectifying diodes, and nonrectifying devices as a consequence of diverse band‐bending at the heterojunction. Diversity in band‐bending near heterojunction is attributed to change in the Fermi level difference (Δ) between BP and ReS₂ sides as a consequence of Φ _BP modulation. No change in the current transport characteristics in several devices with fixed Δ also provides further evidence that current‐transport is substantially impacted by band‐bending at the heterojunction. Optoelectronic experiments on the Esaki diode and the p–n junction diode provide experimental evidence of band‐bending diversity. Additionally, the p⁺–n–p junction comprising BP (38 nm)/ReS₂/BP(5.8 nm) demonstrates multifunctionality of binary and ternary inverters as well as exhibiting the behavior of a bipolar junction transistor with common‐emitter current gain up to 50.     

Demonstration of logic AND device using a split-gate pentacene field effect transistor

We report on the fabrication and performance of pentacene-based split-gate field effect transistors (FETs) on doped Si/SiO₂ substrates. Several transistors with split gate structures were fabricated and demonstrated AND logic functionality. The transistor’s functionality was controlled by applying either 0 or − 10 V to each of the gate electrodes. When − 10 V was simultaneously applied to both gates, the transistor was conductive (ON), while any other combination of gate voltages rendered the transistor highly resistive (OFF). A significant advantage of this device is that AND logic devices with multiple inputs can be built using a single pentacene channel with multiple gates. The p-type carrier mobility of charge within the pentacene active layer of these transistors was about 10^− 5 cm²/V-s. We attribute the low value of mobility primarily to the sharp contours of the pentacene film between the drain and the source contacts and to defects in the pentacene film. The average charge density was 1.4 × 10¹² holes/cm². Despite low mobility, the devices operated at lower drain-source (V_DS) and gate-source (V_GS) voltages as compared with previously reported pentacene based FETs.     

A High‐Performance Top‐Gated Graphene Field‐Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric

A high‐performance top‐gated graphene field‐effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface‐energy‐engineered copolymer gate dielectric via a solvent‐free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane and 1‐vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p‐doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (V_Dirac) of the graphene FET can thus be systematically controlled. In particular, the V_Dirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field‐effect hole and electron mobility values of over 7200 and 3800 cm² V^?1 s^?1, respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high‐frequency flexible device applications.     

Tunable Schottky diodes fabricated from crossed electrospun SnO2/PEDOT-PSSA nanoribbons

Schottky diodes have been fabricated on doped Si/SiO₂ substrates in air, by simply crossing individual electrospun tin oxide (SnO₂) and poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonate) (PEDOT-PSSA) nanoribbons. The conductivity of PEDOT-PSSA was ∼6 S/cm with no observable field effect, while SnO₂ exhibited n-doped field effect behavior with a charge mobility of ∼3.1 cm²/V-s. The diodes operate in air or in vacuum, under ambient illumination or in the dark, with low turn-on voltages and device parameters that are tunable via a back gate bias or a UV light source. Their unique design involves a highly localized active region that is completely exposed to the surrounding environment, making them potentially attractive for use as sensors. The standard thermionic emission model of a Schottky junction was applied to analyze the forward bias diode characteristics and was successfully tested as a half wave rectifier.