H.264熵解码器CAVLC的硬件设计

H.264/AVC是ITU-T和MPEG组织共同推出的最新一代视频压缩标准,其压缩效率较H.263和MPEG-4 simple profile有显著提高.     

High-speed CAVLC encoder for H.264/AVC using parallel zig-zag scanning

A high-speed context-based adaptive variable length coding (CAVLC) encoder for H.264/AVC is presented. Since CAVLC scans residues in a block one by one to obtain the statistics of the data to be encoded, it requires a large number of cycles. In the proposed scheme, two residues are scanned in one cycle to reduce scanning time by half.     

H.264/AVC中CAVLC编码器的硬件实现

设计了一种适用于H.264/AVC标准的CAVLC硬件编码器,在电路实现中将编码流程并行处理,安排了紧凑的控制时序,同时针对算法原理设计了提取数据特征的专用电路单元,减少了后续模块运算的复杂性,从而完成了数据的高效编码。仿真结果表明,在工作频率181 MHz的情况下,设计的数据吞吐率为41.97 Msample/s。在SMIC 0.18μm工艺下综合结果显示,最大频率为181 MHz时,电路规模为2 660门。     

High Throughput Parallel Decoding Method for H.264/AVC CAVLC

A high throughput parallel decoding method is developed for context‐based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical‐operation‐based parallel decoder for M=8 and a conventional parallel decoder. High‐speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.     

Linear-time prediction mode reduction method for intracoding in H.264/AVC

We present a linear-time elimination method to adaptively reduce the nine intraprediction modes in H.264/AVC to two, three, five, or nine modes while preserving a satisfactory reconstructed video quality. Resemblance between prediction modes and appearing frequency for each prediction mode are first determined in an off-line way from the training video sequences. Prediction modes are modeled as vertices and resemblance between two prediction modes as the weight of the connecting edge in a complete graph. Then, find the Hamilton cycle with the minimum sum of weights. When encoding each intrablock, prediction modes corresponding to the adjacent vertices along the Hamilton cycle are examined for similarity. The prediction mode which appears less frequently in a pair of similar prediction modes is declared as redundant and eliminated. When compared with Laroche et al.’s method which aims to reduce the bitrate, experimental results demonstrate that the proposed elimination method can substantially reduce the execution time while preserving the peak signal-to-noise ratio and bitrate performance.     

Efficient coding of motion vector and mode information for H.264/AVC

This paper aims to reduce the size of header in H.264; therefore we only focus on compressing the larger header data into small one. H.264/AVC is the newest video coding standard, which adopts some new techniques to improve the compression efficiency. However, H.264 gets larger header than those of previous standards because the techniques exploit in detail the content of input image. The most parts of header are composed of macroblock type (mb_type) and motion vector difference (mvd), and there are redundancies in the header of H.264. Especially, when mode 8 is selected during mode decision at macroblock level, all four sub-macroblock data are transferred into bitstream. Building the idea above, we propose the scheme using the type code and quadtree to solve the problems. Experimental results show that our algorithm achieved lower total number of encoded bits over JM14.2 up to 31.87% bit reduction at QP 40 on average.     

H.264/AVC视频编码标准中CAVLC解码器的设计

提出了一种应用于H.264/AVC的快速低功耗CAVLC解码器设计方法.对较复杂的几个模块进行了算法和结构上的优化,减少了占用的硬件资源,降低了实现复杂性.仿真结果表明:采用该方法设计的解码器可以正确解码每个变换块中的变换系数,且能在一个时钟周期解出一个句法,完全可以满足H.264视频实时解码的要求.     

基于SoC平台设计的H.264/AVC CAVLC解码器

提出了一种基于SoC平台的CAVLC解码器.在尽量减少时钟消耗的前提下,此解码器可以解码每个变换块中变换系数的熵编码码流,并将结果按照块扫描顺序并行输出.通过在XILJNX的ISE6.0 FPGA开发软件下仿真及分析表明,在120MHz时钟时可以满足10 Mb/s码率下H.264标准中Level3.0的性能要求.     

Design of High‐Speed CAVLC Decoder Architecture for H.264/AVC

In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.     

用于内容认证的VLC域的 H.264/AVC视频水印方案

A semi-fragile content authentication algorithm is proposed for low bit-rate H.264/AVC video in VLC domain. Utilizing the intra prediction mode and coded block pattern in VLC domain, the proposed algorithm chooses those macro-blocks from which the signature is extracted and constructs content signature at macro-block level according to the relationship among the energies of quantized low-frequency coefficients of sub-macroblocks. The signature is embedded by modifying the trailing coefficients. The experimental results show that the proposed algorithm performs well in visual quality impact and keep the bit-rate basically unchanged. In addition, the algorithm can embed signatures into I, P, B slices simultaneously and remarkably enhances the watermark capacity. By verifying the extracted signature, the algorithm can detect and locate video tampering efficiently.     

A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

This paper proposes a novel cost-effective and programmable architecture of CAVLC decoder for H.264/AVC, including decoders for Coeff_token, T1_sign, Level, Total_zeros and Run_before. To simplify the hardware architecture and provide programmability, we propose four new techniques: a new group-based VLD with efficient memory (NG–VLDEM) for Coeff_token decoder, a novel combined architecture (NCA) for level decoder, a new group-based VLD with memory access once (GMAO) for Total_zeros decoder and a new VLD architecture based on multiplexers instead of searching memory (MISM) for Run_before decoder. With the above four techniques, the proposed CAVLC decoder can decode every syntax element within one clock cycle. Synthesis result shows that the hardware cost is 3,310 gates with 0.18 μm CMOS technology at a clock constrain of 125 MHz. Therefore, the proposed design is satisfied for real-time applications, such as H.264/AVC HD1080i video decoding.

Steganalysis of prediction mode modulated data-hiding algorithms in H.264/AVC video stream

In the intra-frame coding of H.264/AVC, information hiding can be implemented by modulating the prediction modes of 4?×?4 luminance blocks. Because such kind of methods has characteristics of high speed, good concealment, and so on, it is very suitable to build the covert communication system based on video communications and brings a great public security threat. Therefore, it is important to study its steganalysis method. In this paper, we first analyzed the changes of remarkable characteristics in intra-frame coding caused by modulating intra-prediction modes for information hiding, and found that the inherent correlation among the prediction modes in different 4?×?4 luminance blocks belonging to an intra-frame coding macroblock was changed. According to several different positional relationships of the adjacent 4?×?4 blocks in spatial domain, we designed statistical models corresponding to the prediction mode correlation to make quantitative extraction of these correlation characteristics. An information hiding detector was constructed based on the support vector machine. Based on the constructed detector, the experimental results show that the mean of the detection accuracy, recall ratio, and precision ratio are all excellent for different test video sequences.     

一种基于H.264/AVC帧内预测模式选择的快速算法

依据宏块的空间相关性,并从概率的角度考虑,提出了一种新的快速模式选择算法,该方法减少了对Intra4×4和Intra16×16的预测模式率失真的计算,降低了帧内预测编码的复杂度.与参考软件JM11.0中模式选择算法相比,在PSNR基本保持不变的情况下,新算法的编码时间缩短了大约30%,而比特率仅提高了1%左右.     

Novel H.264/AVC entropy coding mode decision

In this work, we propose a novel entropy coding mode decision algorithm to balance the tradeoff between the rate-distortion (R-D) performance and the entropy decoding complexity for the H.264/AVC video coding standard. Context-based adaptive binary arithmetic coding (CABAC), context-based adaptive variable length coding (CAVLC), and universal variable length coding (UVLC) are three entropy coding tools adopted by H.264/AVC. CABAC can be used to encode the texture and the header data while CAVLC and UVLC are employed to encode the texture and the header data, respectively. Although CABAC can provide better R-D performance than CAVLC/UVLC, its decoding complexity is higher. Thus, by taking the entropy decoding complexity into account, CABAC may not be the best tool, which motivates us to examine the entropy coding mode decision problem in depth. It will be shown experimentally that the proposed mode decision algorithm can help the encoder generate the bit streams that can be decoded at much lower complexity with little R-D performance loss.     

Adaptive slice-level parallelism for H.264/AVC encoding using pre macroblock mode selection

In order to achieve high computational performance and low power consumption, many modern microprocessors are equipped with special multimedia instructions and multi-core processing capabilities. The number of cores on a single chip increases double every three years. Therefore, besides complexity reduction by smart algorithms such as fast macroblock mode selection, an effective algorithm for parallelizing H.264/AVC is also very crucial in implementing a real-time encoder on a multi-core system. This algorithm serves to uniformly distribute workloads for H.264/AVC encoding over several slower and simpler processor cores on a single chip. In this paper, we propose a new adaptive slice-size selection technique for efficient slice-level parallelism of H.264/AVC encoding on a multi-core processor using fast macroblock mode selection as a pre-processing step. For this we propose an estimation method for the computational complexity of each macroblock using pre macroblock mode selection. Simulation results, with a number of test video sequences, show that, without any noticeable degradation, the proposed fast macroblock mode selection reduces the total encoding time by about 57.30%. The proposed adaptive slice-level parallelism has good parallel performance compared to conventional fixed slice-size parallelism. The proposed method can be applied to many multi-core systems for real-time H.264 video encoding.     

Parallel fast inter mode decision for H.264/AVC encoding

For H.264/AVC encoding, the mode selection process consumes a large proportion of the overall computation. To reduce this burden, various fast mode decision algorithms have been proposed. The current fast mode decision algorithms usually exploit the relationship among the coding modes and use the context-based approach to reduce the number of modes to be checked for both intra coding and inter coding. The parallel capacity of hardware architectures are also taken into consideration. However, almost all the parallel fast mode decision designs are focusing on intra coding. In this paper, a hardware friendly parallel fast inter mode decision method is proposed. With the proposed method, the inter mode decision can be conducted efficiently in one pass and significant encoding speedup can be achieved with negligible coding efficiency loss. Moreover, the proposed method can be easily mapped to hardware architecture which can be used for the real-time video encoding.     

Efficient information hiding in H.264/AVC video coding

This paper proposes a new real-time information hiding algorithm on latest H.264/AVC video coding standard. The information is embedded into the Trailing Ones of 4×4 blocks during the Context-based Adaptive Variable Length Coding (CAVLC) process. This algorithm is efficient with low computational complexity. The simulation results show that the degradation of video quality is negligible, and the same overall bit-stream length is maintained. Based on this information hiding method, a video subtitle transmission scheme is proposed. Under the simulation of different RTP packet loss channels, the embedded information can be well recovered. The comparison with other algorithms shows the superiority of our proposed method.     

Improved macroblock mode selection for H.264/AVC in wireless environments

An improved macroblock mode selection method based on the ROPE algorithm is proposed for the H.264/AVC encoder. The proposed method avoids the recursive calculation of second moment values by using the standard deviation. Simulation results show much improved performance over the method in the current H.264/AVC reference encoder.     

Enhanced pipelined architecture of H.264/AVC intra prediction

This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18 µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56 MHz.     

Fast mode decision algorithm for intra prediction in H.264/AVC with integer transform and adaptive threshold

Compared with other existing video coding standards, H.264/AVC can achieve a significant improvement in compression performances. A robust criterion named the rate distortion optimization (RDO) is employed to select the optimal coding modes and motion vectors for each macroblock (MB), which achieves a high compression ratio while leading to a great increase in the complexity and computational load unfortunately. In this paper, a fast mode decision algorithm for H.264/AVC intra prediction based on integer transform and adaptive threshold is proposed. Before the intra prediction, integer transform operations on the original image are executed to find the directions of local textures. According to this direction, only a small part of the possible intra prediction modes are tested for RDO calculation at the first step. If the minimum mean absolute error (MMAE) of the reconstructed block corresponding to the best mode is smaller than an adaptive threshold which depends on the quantization parameter (QP), the RDO calculation is terminated. Otherwise, more possible modes need to be tested. The adaptive threshold aims to balance the compression performance and the computational load. Simulation results with various video sequences show that the fast mode decision algorithm proposed in this paper can accelerate the encoding speed significantly only with negligible PSNR loss or bit rate increment. This work is supported in part by China National Natural Science Foundation (CNSF) under Project No.60572045, the Ministry of Education of China Ph.D. Program Foundation under Project No.20050698033, and by a Cooperation Project (2005.7– 2007.7) with Microsoft Research Asia.