Reconfigurable SiGe Low-Noise Amplifiers With Variable Miller Capacitance

A new input matching method making use of shunt-shunt feedback capacitance is introduced. Based on the new input matching method, reconfigurable SiGe low-noise amplifiers (LNAs) by varying shunt-shunt feedback capacitance are proposed. Two approaches are used to vary the shunt-shunt feedback capacitance. One approach is to switch between two different bias currents while the other is to use a series combination of a switch and a capacitor. Miniaturized fully monolithic reconfigurable SiGe LNAs without emitter degenerative inductors were realized by the above two approaches. The reconfigurable SiGe LNA achieved by switching bias currents only occupies a very small area of 355 mumtimes155 mum, excluding measurement pads. This LNA achieves an input return losses (S₁₁) of -27.6 dB, a voltage gain (A _v) of 19.8 dB, and a noise figure (NF) of 3.18 dB for 2.4-GHz band when biased at a current of 3.8 mA and can be reconfigured to obtain A_v=20.4/20.3 dB, S₁₁=-47.1/-24.6 dB and NF=3.42/3.21 dB for 5.2/5.7-GHz band when bias current is switched to 3 mA. In addition, a 2.4/4.9/5.2/5.7-GHz reconfigurable SiGe LNAs for WLAN applications, whose variable shunt-shunt feedback capacitance is controlled by a switch and a capacitor, was also realized     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

0.18 μm 21-27 GHz CMOS UWB LNA with 9.3 ± 1.3 dB gain and 103.9 ± 8.1 ps group delay

A 21-27 GHz CMOS ultra-wideband low-noise amplifier (UWB LNA) with state-of-the-art phase linearity property (group delay variation is only ± 8.1 ps across the whole band) is reported for the first time. To achieve high and flat gain (S₂₁) and small group delay variation at the same time, the inductive series peaking technique was adopted in the output of each stage for bandwidth enhancement. The LNA dissipated 27 mW power and achieved input return loss (S₁₁) of 213 to 220.1 dB, output return loss (S₂₂) of 28.2 to 230.2 dB, flat S21 of 9.3 ± 1.3 dB, reverse isolation (S₁₂) of 252.7 to 273.3 dB, and noise figure of 4.9?6.1 dB over the 21-27 GHz band of interest. The measured 1 dB compression point (P_1dB) and input third-order intermodulation point (IIP3) were 214 and 24 dBm, respectively, at 24 GHz.     

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S₁₁ below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs     

3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique

In this paper, we demonstrate an SiGe HBT ultra-wideband (UWB) low-noise amplifier (LNA), achieved by a newly proposed methodology, which takes advantage of the Miller effect for UWB input impedance matching and the inductive shunt-shunt feedback technique for bandwidth extension by pole-zero cancellation. The SiGe UWB LNA dissipates 25.8-mW power and achieves S₁₁ below -10 dB for frequencies from 3 to 14 GHz (except for a small range from 10 to 11 GHz, which is below -9 dB), flat S₂₁ of 24.6 plusmn 1.5 dB for frequencies from 3 to 11.6 GHz, noise figure of 2.5 and 5.8 dB at 3 and 10 GHz, respectively, and good phase linearity property (group-delay variation is only plusmn28 ps across the entire band). The measured 1-dB compression point (P₁ dB) and input third-order intermodulation point are -25.5 and -17 dBm, respectively, at 5.4 GHz.     

0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

3-10 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

A CMOS distributed amplifier (DA) with flat and low noise figure (NF), and flat and high gain (S ₂₁) is demonstrated. A flat and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S ₂₁ was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S ₂₁ of 17.5 plusmn 1.23 dB with an average NF of 3.24 dB over the 3-10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S ₂₁ of 10.74 plusmn 1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW.     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range     

First demonstration of monolithic InP-based HBT amplifier with PNPactive load

An InP-based integrated HBT amplifier with PNP active load was demonstrated for the first time using complementary HBT technology (CRBT). Selective molecular beam epitaxy (MBE) regrowth was employed and a merged processing technology was developed for the monolithic integration of InP-based NPN and PNP HBTs on the same chip. The availability of PNP devices allowed design of high gain amplifiers with low power supply voltage. The measured amplifier with PNP HBT active load achieved a voltage gain of 100 with a power supply (V_CC) of 1.5 V. The corresponding voltage swing was 0.9 V to 0.2 V. The amplifier also demonstrated S₂₁ of 7.8 dB with an associated S₁₁ and S₂₂ of -9.5 dB and -8.1 dB, respectively, at 10 GHz     

Integrated metal magnetic film coupled line circulators for monolithic microwaveintegrated circuits

A new structure of integrated planar metal magnetic film coupled line (MMFCL) circulators is presented, in which a metal magnetic film is used instead of ferrite materials. Simulation was performed with HFSS based on coupled-mode theory. An insertion loss of 4 dB and isolation of -13.5 dB between S₂₁ and S₁₂ over a frequency band of 3 GHz (from 36.5 to 39.5 GHz) were realised for a three-port MMFCL circulator     

Design of active phase shifters based on multichannelheterojunction field effect transistors (MCHFET's)

Design criteria of active phase shifters based on GaAs/AlGaAs multichannel (MC) HFET in the frequency range 4-60 GHz are presented. The phase characteristics of MCHFET devices were studied using the computer aided design program TOUCHSTONE. The dependence of transmission phase on various intrinsic elements in the equivalent circuit model as a function of control gate bias was also studied. There are limited gate bias ranges which correspond to the active regions of the two conducting wells for which a quasi-linear continuous phase shift for analog applications was achieved. Continuously varying the gate bias from V_gs=-1.9 V to V_gs=-0.6 V results in a quasilinear phase shift of 10°, 15°, 21°, and 29° at f=12, 20, 30, and 60 GHz, respectively. Similarly, varying the gate bias from V_gs =-0.4 V to V_gs=0.7 V a quasi-linear phase shift of 21°, 26°, 27°, and 23° at f=12, 20, 30, and 60 GHz, respectively, was achieved. The gain variation was less than 3 dB in these bias regions. With digital applications in mind, a maximum differential phase shift of around 50° was obtained by switching the gate bias discretely. The transmission phase of single gate MCHFET mostly depends on variation of gate source capacitance with gate bias rather than on other intrinsic elements. The dependence of phase shift on various geometrical and structural parameters is also presented. To test the practicality of the device, other scattering parameters (e.g., S₁₁, S₂₂, S₁₂) and the noise figure (NF) were finally studied     

A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power

This paper reports on a S-, C-band low-noise power amplifier (LNPA) which achieves a sub-0.2 dB noise figure (NF) over a multi-octave band and a saturated output power (Psat) of 2 W at a cool temperature of -30degC . The GaN MMIC is based on a 0.2 mum AlGaN/GaN-SiC HEMT technology with an f_T ~ 75 GHz. At a cool temperature of -30degC and a power bias of 15 V-400 mA, the MMIC achieves 0.25-0.45 dB average NF over a 2-8 GHz band and a linear P_1dB of 32.8 dBm ( ~ 2 W) with 25% power-added efficiency (PAE). At a medium bias of 12 V-200 mA, the amplifier achieves 0.1-0.2 dB average NF across the same band and a P_1dB of 32.2 dBm (1.66 W) with 35% PAE. The corresponding saturated output power is greater than 2 W. At a low noise bias of 5 V-200 mA, a remarkable 0.05-0.15 dB average NF is achieved with a P_1dB > 24 dBm and PAE ~ 33%. These results are believed to be the lowest NF ever reported for a multi-octave fully matched MMIC amplifier capable of > 2 W of output power.     

应用于GSM/EDGE零中频接收机的CMOS射频前端

介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90...     

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S₁₁ of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.     

Broad-band dual-polarized single microstrip patch antenna with highisolation and low cross polarization

This paper presents a new design of a broad-band dual-polarized single microstrip patch antenna with highly decoupled input ports and low cross-polarization (XP) radiation. A prototype of the proposed antenna with center frequency at 1800 MHz is presented. Both the dual linear polarizations have 10-dB return-loss impedance bandwidths greater than 14% and high decoupling between the two input ports (S₂₁ less than -40 dB across the entire bandwidths) is obtained. Moreover, the XP radiation in the principal planes of the dual linear polarizations is seen to be less than -20 dB     

Design optimization and characterization of high-gain GaInP/GaAsHBT distributed amplifiers for high-bit-rate telecommunication

The design methodology, processing technology, and characterization of high-gain GaInP/GaAs heterojunction-bipolar-transistor-based distributed amplifiers are described in this paper. Distributed amplifiers with different active cells and number of stages have been compared for high-gain (>12 dB) and high-bandwidth (>25 GHz) performance. Based on the results, a three-stage attenuation-compensated distributed amplifier with a flat gain (S₂₁) of 12.7 dB over a bandwidth of 27.5 GHz was successfully fabricated and tested. Eye-diagram tests at 10 Gb/s show very open eye characteristics with no signal skewing. The amplifier achieves a minimum noise figure of 4 dB at 3 GHz and a sensitivity of -25 dBm for 10-Gb/s nonreturn-to-zero 2¹⁵-1 pseudorandom bit sequence with a bit error rate of 10^-9     

A Ka-Band CMOS Wilkinson Power Divider Using Synthetic Quasi-TEM Transmission Lines

This work presents a Ka-band two-way 3 dB Wilkinson power divider using synthetic quasi-transverse electromagnetic (TEM) transmission lines (TLs). The synthetic quasi-TEM TL, also called complementary-conducting-strip TL (CCS TL), is theoretically analyzed. The equivalent TL model, whose production is based on the extracted results, is applied to the power divider design. The prototype is fabricated by the standard 0.18 mum 1P6M CMOS technology, showing the circuit size of 210.0 mumtimes390.0 mum without contact pads. The measurement results, which match the 50 Omega system, reveal perfect agreements with those of the simulations. The comparison reveals the following characteristics. The divider exhibits an equal power-split with the insertion losses (S₂₁ and S₃₁) of 3.65 dB. The return losses (S₁₁, S₂₂ and S₃₃) of the prototype are higher than 10.0 dB from 30.0 to 40.0 GHz.     

Fabrication and Characteristics of 40-Gb/s Traveling-Wave Electroabsorption Modulator-Integrated DFB Laser Modules

We have developed 40-Gb/s traveling-wave electroabsorption-modulator-integrated distributed feedback laser (TW-EML) modules using several advanced technologies. First, we have adopted a selective area growth (SAG) method in the fabrication of the 40-Gb/s EML device to provide active layers for the laser and the electroabsorption modulators (EAMs) simultaneously. The fabricated device shows that the measured 3-dB bandwidth of electrical-to-optical (E/O) response reaches about 45 GHz and the return loss (S₁₁) is kept below -10 dB up to 50 GHz. For the module design of the device, we mainly considered electrical and optical factors. The measured S₁₁ of the fabricated 40 Gb/s TW-EML module is below -10 dB up to about 30 GHz and the 3-dB bandwidth of the E/O response reaches over 35 GHz. We also have developed two types of coplanar waveguide (CPW) for the application of the driver amplifier integrated 40 Gb/s TW-EML module, which is a system-on-package (SoP) composed of an EML device and a driver amplifier device in a module. The measured S₁₁ of the two-step-bent CPW is below -10 dB up to 35 GHz and the measured S₁₁ of the parallel type CPW is below -10 dB up to 39 GHz.     

高增益K波段MMIC低噪声放大器

基于0.25μm PHEMT工艺,给出了两个高增益K波段低噪声放大器.放大器设计中采用了三级级联增加栅宽的电路结构,通过前级源极反馈电感的恰当选取获得较高的增益和较低的噪声;采用直流偏置上加阻容网络,用来消除低频增益和振荡;三级电路通过电阻共用一组正负电源,使用方便,且电路性能较好,输入输出驻波比小于2.0;功率增益达24dB;噪声系数小于3.5dB.两个放大器都有较高的动态范围和较小的面积,放大器1dB压缩点输出功率大于15dBm;芯片尺寸为1mm×2mm×0.1mm.该放大器可以应用在24GHz汽车雷达前端和26.5GHz本地多点通信系统中.     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.