Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.     

Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

The electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs (FXMOSFETs) fabricated by a wet process have experimentally and systematically been investigated. The almost ideal S-slope of 64 mV/decade was obtained for the fabricated 20 nm Si-Fin and 125 nm gate-length FXMOSFET. This excellent subthreshold characteristic shows that the quality of the rectangular Si-Fin channel with (111)-oriented sidewall is good enough to realize high-performance FXMOSFETs. The current and transconductance multiplication accurately proportional to a number of 30 nm Si-Fin channels was confirmed in the fabricated multi-fin FXMOSFETs. The systematic investigation of the electrical characteristics of the fabricated FXMOSFETs in the 20-110-nm Si-Fin and 2.3-5.2-nm gate oxide regimes reveals that short-channel effects can be effectively suppressed by reducing the Si-Fin thickness to 20 nm or less. The developed processes are quite attractive for fabrication of ultranarrow Si-Fin channel double-gate MOSFETs.     

Ambipolar Coulomb blockade characteristics in a two-dimensional Si multidot device

A two-dimensional Si multidot channel field-effect transistor is fabricated from a silicon-on-insulator material and the electrical characteristics are studied. The multidots are formed using a nanometer-scale local oxidation of Si process developed in our laboratory. The device shows ambipolar characteristics because of Schottky source and drain, i.e., the carriers are electrons for positive gate voltage and holes for the negative one. It is shown that Coulomb blockade (CB) oscillations are clearly observed for both of the electrons and holes at measurement temperatures up to 60 K. Both CB characteristics show nonperiodic oscillation and an open Coulomb diamond. These features are ascribed to the single electron/hole tunneling in the Si multidot channel.     

High-Precision Displacement Sensing of Monolithic Piezoelectric Disk Resonators Using a Single-Electron Transistor

A single-electron transistor (SET) can be used as an extremely sensitive charge detector. Mechanical displacements can be converted into charge, and hence, SETs can become sensitive detectors of mechanical oscillations. For studying small-energy oscillations, an important approach to realize the mechanical resonators is to use piezoelectric materials. Besides coupling to traditional electric circuitry, the strain-generated piezoelectric charge allows for measuring ultrasmall oscillations via SET detection. Here, we explore the usage of SETs to detect the shear-mode oscillations of a 6-mm-diameter quartz disk resonator with a resonance frequency around 9 MHz. We measure the mechanical oscillations using either a conventional DC SET, or use the SET as a homodyne or heterodyne mixer, or finally, as a radio-frequency single-electron transistor (RF-SET). The RF-SET readout is shown to be the most sensitive method, allowing us to measure mechanical displacement amplitudes below \(10^{-13}\) m. We conclude that a detection based on a SET offers a potential to reach the sensitivity at the quantum limit of the mechanical vibrations.     

Quantum dots fabricated by selective area MOVPE and their application to single electron devices

A novel method of formation of uniform GaAs quantum dot (QD) structures, using selective area metalorganic vapour phase epitaxy (SA-MOVPE), and their application to single electron transistors (SETs) are demonstrated. The SiN _x -coated substrates having a wire-like opening with three prominences are used. The wire-like opening is aligned in the [110] direction, which corresponds to channel region of SET. AlGaAs/GaAs modulation-doped heterostructures are grown on these substrates. Due to three prominences on the wire, the quasi-one-dimensional electron gas (Q-1DEG) channel, having a periodic variation in its width, are naturally formed. This leads to the formation of a quantum dot near the central prominence and two tunneling barriers beside the dot, which are connected to quantum wires.I _D−V _G characteristics under constant source-drain bias condition show clear conductance oscilations near the pinch-off, and oscillations are observed up to 65 K.I _D−V _DS characteristics measured at 2·1 K show clear Coulomb blockade. The results indicate the formation of SET by SA-MOVPE. Using similar method, resistance-load single electron inverter circuit is also fabricated.     

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

We investigate the tunneling barrier structures in the room-temperature operating silicon single-electron transistors (SETs). The devices are fabricated in the form of the point-contact channel metal-oxide-semiconductor field-effect transistors with gate oxide formed by thermal oxidation or low-pressure chemical vapor deposition (LP-CVD). From the gate voltage and temperature dependence of the peak current in the SET characteristics, it is found that the thermal oxidation process leads to higher and narrower tunneling barriers. In some SETs with CVD-deposited gate oxide, thermally activated conduction over the low tunneling barriers is clearly observed in a wide temperature range from 100 K-300 K.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.     

垂直沟道器件的研究与进展

介绍了垂直沟道器件的常见结构和工艺，分析了垂直沟道器件的最新进展以及垂直沟道器件制作工艺中的最新技术，详细讨论了垂直沟道器件的性能，并分析了垂直沟道器件的优点以及存在的问题。     

Experimental study of thermomechanical oscillations of a cylindrical heater in an air medium with free convection

It is demonstrated experimentally that when appropriate conditions are fulfilled, oscillations in the heat liberation coefficient of an electrically heated wire vibrating in air are capable of parametrically exciting intense mechanical oscillations in the wire.Translated from Inzhenerno-Fizicheskii Zhurnal, Vol. 37, No. 6, pp. 1051–1053, December, 1979.     

Identical-dual-bandpass sampled fiber Bragg grating and its application to ultranarrow filters

We have theoretically proposed and experimentally demonstrated a new kind of ultranarrow identical-dual-bandpass sampled fiber Bragg gratings (SFBGs) with a pi phase shift technique. The spacing of two bandpasses of the proposed grating can be flexibly adjusted by changing the sampled period, and any desired spacing can be achieved in principle. An experimental example shows that the transmission peaks of two narrow transmission-band are near 1549.1 and 1550.1 nm. Based on the proposed SFBG, an ultranarrow identical-dual-channel filter is designed. Two channels of the proposed filter have an equal bandwidth, an even strength, and the same group delay. The bandwidth of each channel of our filter is as small as 1 pm and up to 10(-3) pm (corresponding to approximately 0.1 MHz), which is less than the bandwidth of the conventional SFBG filters by a factor of 10(2)-10(4). The proposed grating and filter can find potential applications with slow light and dual-wavelength single-longitudinal-mode fiber lasers.     

Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs

The body effect in ultrathin body (silicon-on-insulator) SOI MOSFETs has been investigated by experiments and modeling. It is demonstrated for the first time that the adjustable threshold voltage range by substrate bias is enhanced due to the quantum confinement effect in ultrathin body SOI. The enhancement ratio of the adjustable threshold voltage range in a 4.3-nm-thick SOI MOSFET compared to 11.7-nm-thick one is around 10%. This indicates that ultrathin body MOSFETs are useful not only for suppressing the short channel effects, but also for suppressing the off-leak current in the variable threshold CMOS scheme.     

Design optimization of gate-all-around (GAA) MOSFETs

The design of gate-all-around (GAA) MOSFETs was optimized and compared with that of double-gate MOSFETs. We discussed the optimal ratio of the fin width to the gate length and investigated short-channel effects of GAA MOSFETs. Using three-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as the gate length in GAA MOSFETs. Finally, we compared cubical channel GAA MOSFETs with cylindrical-channel ones. As a result, it was observed that the latter showed the maximized ratio of the fin width to the gate length up to 1.2.     

Highly luminescent (Zn,Cd)Te/CdSe colloidal heteronanowires with tunable electron-hole overlap

We report the synthesis of ultranarrow (Zn,Cd)Te/CdSe colloidal heteronanowires, using ZnTe magic size clusters as seeds. The wire formation starts with a partial Zn for Cd cation exchange, followed by self-organization into segmented heteronanowires. Further growth occurs by inclusion of CdSe. The heteronanowires emit in the 530 to 760 nm range with high quantum yields. The electron-hole overlap decreases with increasing CdSe volume fraction, allowing the optical properties to be controlled by adjusting the heteronanowire composition.     

Tunable ultranarrow linewidth of a cavity induced by interacting dark resonances

A scheme for obtaining a tunable ultranarrow linewidth of a cavity due to an embedded four-level atomic medium with double-dark resonances is proposed. It is shown that the steep dispersion induced by double-dark resonances in the transparency window leads to the ultranarrow transmission peak. Compared with the case of a single-dark resonance system, the linewidth can be narrowed even by one order under proper conditions. Furthermore, the position of the ultranarrow peak can be engineered by varying the detuning of the control field.     

Spin Injection Efficiency at the Source/Channel Interface of Spin Transistors

Almost all spintronic transistors (e.g., spin field-effect transistors, spin bipolar transistors, and spin-enhanced MOSFETs) require high efficiency of spin injection from a ferromagnetic contact into a semiconductor channel for proper operation. In this paper, we calculate the efficiency of spin injection from a realistic nonideal ferromagnetic contact into the semiconductor quantum wire channel of a spintronic transistor, taking into account the presence of an axial magnetic field (caused by either the ferromagnetic contact or external agents) and spin orbit interaction. In our calculations, the temperature is assumed to be low enough that phonon scattering is weak and transport is phase-coherent, although not ballistic because of elastic scattering caused by impurities and defects. We consider a single impurity in the channel and show that the conductance depends strongly on the exact location of this impurity because of quantum mechanical interference effects. This is a nuisance since it exacerbates device variability. The ldquosignrdquo of the impurity potential, i.e., whether it is attractive or repulsive, also influences the channel conductance. Surprisingly, at absolute zero temperature, the spin injection efficiency can reach 100% at certain gate biases, even though the ferromagnetic injector is nonideal. However, this efficiency drops rapidly with increasing temperature.     

Data transmission through a radio channel using masking oscillations

A scheme of data transmission through a radio channel masked by chaotic oscillations is considered. A mathematical model describing the system is formulated in the case of chaotic oscillations generated in two separated frequency bands. The results of a numerical analysis of the model are presented. It is demonstrated that hidden data transmission in such a channel is possible.     

Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND (OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area     

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.     

Integration of single-electron transistors using field-emission-induced electromigration

A novel technique for the integration of planar-type single-electron transistors (SETs) composed of nanogaps is presented. This technique is based on the electromigration procedure, which is caused by a field emission current. The technique is called "activation." By applying the activation to the nanogaps, SETs can be easily obtained. Furthermore, the charging energy of the SETs can be controlled by adjusting the magnitude of the applied current during the activation process. The integration of two SETs was achieved by passing a field emission current through two series-connected initial nanogaps. The current-voltage (I(D)-V(D)) curves of the simultaneously activated devices exhibited clear electrical-current suppression at a low-bias voltage at 16 K, which is known as the Coulomb blockade. The Coulomb blockade voltage of each device was also obviously modulated by the gate voltage. In addition, the two SETs, which were integrated by the activation procedure, exhibited similar electrical properties, and their charging energy decreased uniformly with increasing the preset current during the activation. These results indicate that the activation procedure allows the simple and easy integration of planar-type SETs.