Numerical simulation on novel FinFETs: asymmetric poly-silicon gate FinFETs and TiN gate FinFETs

We report our numerical study on the device performance of an asymmetric poly-silicon gate FinFET and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-silicon FinFET structure and TiN gate FinFET structures exhibit superior V _T tolerance over the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V _T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation further revealed that the threshold voltage (V _T) can be controlled within the range of −0.1∼+0.5 V through varying the doping concentration of the asymmetric poly-silicon gate region from 1.0×10¹⁸ to 1.0×10²⁰ cm⁻³.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

Continued scaling of transistors into the nanoscale regime has led to large device-to-device variation in transistor characteristics. These variations reflect differences in substrate doping, channel length, interface and/or oxide defects, etc. among various transistors. In this paper, we develop a theory for the statistical distribution of threshold voltage degradation (ΔV _T ) due to the Negative Bias Temperature Instability (NBTI). First, we model the time dynamics of interface defects within the Reaction-Diffusion (R-D) framework and calculate the statistics of interface defect using Markov Chain Monte-Carlo method. We show that the generation and annealing of interface defects are strongly correlated and that the statistics of interface defect at a given stress time (N _IT @t _STS ) follows a skew-normal distribution. Second, we explore the differential effect of the spatial distribution of interface defects in nanoscale transistors pre-populated with a discrete number of randomly placed substrate dopants. We model the effect of spatial distribution of defects using a percolative network and demonstrate that the distribution of threshold voltage degradation for a single additional interface defect, i.e., ΔV _T @ΔN _IT =1, is exponential, with a fraction of transistors having ΔV _T ∼0. Finally, we obtain the statistics of ΔV _T @t _STS by convolving the statistics of N _IT @t _STS with that of ΔV _T @ΔN _IT =1. The resultant statistics of ΔV _T @t _STS compares favorably with a broad range of experiments reported in the NBTI literature.     

Ferroelectric properties of (Bi3.15 Nd 0.85 )Ti 3 O 12 with decreasing film thickness

Film texture and ferroelectric behaviors of (Bi_3.15Nd_0.85)Ti₃O₁₂ (BNdT) of layered-perovskite structure deposited on Pt/TiO₂/Si substrate are dependent on the film thickness. When the film thickness is reduced from ∼240 to ∼120 nm, BNdT grains evolve from a rod-like morphology to a spherical morphology, accompanied by a decrease in average grain size. At the same time, P-E hysteresis transforms from a square-shaped hysteresis loop (2Pr ∼24.1 μC/cm² at 240 nm) to a relative slimmer hysteresis loop (with a lower 2Pr = 19.8 μC/cm² at 120 nm). The nonvolatile polarization (Δ P) shows a maximum at the film thickness of 160 nm, where Δ P was measured to be 14.7 μC/cm² and 6.8 μC/cm² at 5 V and 3 V, respectively. A small amount of excess bismuth in the film thickness of 130 nm, introduced by co-sputtering, can lead to a much enhanced remanent polarization (2Pr of 21.3 μC/cm² at 5 V and 15.2 μC/cm²at 3 V), which is promising for low voltage FRAM applications.     

Full Band Monte Carlo Simulation of Wurtzite AlGaN/GaN MODFETs

We present full band Monte Carlo simulations of a wurtzite Al_0.15Ga_0.85N/GaN modulation-doped field-effect transistor (MODFET). We found that without inclusion of the piezoelectric effect, the electron concentrations in the channel are much lower than obtained from experimental data. The calculated I _ds-V _ds curves show a strong negative differential resistance, which is a feature observed in experimental devices. Self-heating effects are usually believed to be the main cause of the negative differential resistance. Our simulations do not include self-heating, and this would indicate that at least part of what is observed is also caused by the drift-velocity behavior vs. electric field of the narrow conduction channel. For a 0.2 m gate MODFET, the simulations yield a maximum trans-conductance G _m 250 mS/mm with V _G = 1.0 V and V _ds = 5.0 V. When V _G = 0.0 V and V _ds = 8.0 V, we obtain a maximum cutoff frequency f _T = 180 GHz with I _d = 1159 mA/mm.     

Tunability and leakage currents of (Ba,Sr)TiO3 ferroelectric ceramics with various additives

The Ba_xSr_{1 − x} TiO₃ ferroelectric ceramics with magnesium (BSM) and neodymium (BSN) additives were studied. Measurements were made of tunability, dielectric losses (tan δ), leakage currents, the correlations between current-voltage I(U) and capacitance-voltage C(U) characteristics. I(U) characteristics of high quality BSM ceramics have four regions: Ohmic, where the conductivity is linear; the horizontal region (or negative differential resistivity); the exponential dependence; and the vertical current enhancement. These BSM samples (∼20% Mg additives) were distinguished by highest breakdown strength (more than 1000 V), low tan δ (less than 10^{− 3} at 1 MHz) and high tunability (up to 10% at E _max∼2 V/μm).     

Simulation of slow current transients and current collapse in GaN FETs

Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V _D is raised abruptly (while keeping the gate voltage V _G constant), the drain current I _D overshoots the steady-state value, and when V _D is lowered abruptly, I _D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V _D and V _G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V _D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.     

Microstructural and electrical properties of multicomponent varistor ceramics with PbO–ZnO–B2O3 glass addition

Zinc oxide based ceramics are widely used materials in varistors because of their excellent nonlinearity. Traditionally these ceramics are sintered at high temperatures (about 1,100–1,300°C). In this work a novel zinc oxide-based material with a low sintering temperature (900–1,000°C) was investigated. This material can be used in varistors consisting of several ceramic layers with embedded silver/palladium thick-film electrodes. This paper explains the research procedure employed with this novel varistor material, including the effect of sintering aid addition on the final electrical properties and fired microstructure. The electrical properties achieved are compared to the values measured from the original zinc oxide composition without sintering aid addition. Especially the I–V characteristics, nonlinearity coefficient α, breakdown voltage V _bk and leakage current density J _L are investigated. The sintering properties are also reported. It was found that by adding 10 wt.% of glass and using a 900 °C sintering temperature, the material had good varistor characteristics, as V _bk = 378 V/mm, α = 33 and J _L  = 15 μA/cm². The investigated varistor material can be applied to protect electrical circuits against surges.     

Comparison of calculated and measured I–V curves for DNA

Cohen et al. have reported experimental observations of current passing through the dsDNA molecules using a metal-covered atomic force microscope (AFM) tip; the molecules are chemically connected to a metal substrate at one end and to a gold nanoparticle (GNP) at the opposite end. They have presented evidence for charge transport through dsDNA molecules of a complex sequence, 26 bp long, characterized by S-shaped current–voltage (I–V) curves. In this paper, theoretical calculations giving excellent agreement with the results of Cohen et al. are obtained using the formalism of Datta et al.     

Comparison of calculated and measured I–V curves for DNA

Cohen et al. have reported experimental observations of current passing through the dsDNA molecules using a metal-covered atomic force microscope (AFM) tip; the molecules are chemically connected to a metal substrate at one end and to a gold nanoparticle (GNP) at the opposite end. They have presented evidence for charge transport through dsDNA molecules of a complex sequence, 26 bp long, characterized by S-shaped current–voltage (I–V) curves. In this paper, theoretical calculations giving excellent agreement with the results of Cohen et al. are obtained using the formalism of Datta et al.     

Ferroelectric-Gate Field Effect Transistors Using (Y,Yb)MnO3/Y2O3/Si(111) Structures for 1T-Type FeRAMs

Fabrication and characterization of metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFIS FETs) using (Y,Yb)MnO₃/Y₂O₃/Si structures were introduced for the first time. P-channel MFIS FETs were fabricated on n-type Si(111) substrates, in which an Y_0.5Yb_0.5MnO₃(200 nm)/Y₂O₃(25 nm) structure was used as gate insulator. The Y_0.5Yb_0.5MnO₃ and Y₂O₃ films were prepared by chemical solution deposition. A fabricated MFIS FETs showed the hysteresis loop due to spontaneous polarization in the I_D-V_GS characteristic, in which the memory window was about 0.9V when the applied gate voltage was swept between 8 V and ?8 V. Especially, the alternative drain current was retained after applying a single voltage pulse with a magnitude of +9 V or ?9 V.     

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

This paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (t_ox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_{C_AVG}, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (T_{C_AVG} = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_DD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.     

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (R_ON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit \( \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) \) are 1140 V, 0.587 mΩ cm² (V_GS = 15 V, V_DS = 1 V), and 2.214 GW/cm², respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).     

Fast-switching-speed,low-forward-voltage-drop static induction (SI) thyristor

A static induction (SI) thyristor using a normally-off planar-gate structure in a low power class has been developed to be used as a power switching device in a three-phase inverter circuit. A 600 V-15 A class SI thyristor with very fast switching time (tgt, tgq) and low forward voltage drop (V_TM) was designed and created. This design was performed with a reasonable wafer structure (n^?/n/p⁺), an n^? base carrier concentration and thickness, and a gate structure (gate diffusion length and gate-gate pitch). Microscopic processing was used to obtain this SI thyristor. The performance trade-off between turn-off time and forward voltage drop is controlled by a lifetime control process using proton irradiation that results in a very fast switching time with tgt of 500 ns and tgq of 500 ns with V_TM of 1.5 V (at I_T= 18 A). At a current level of I_T = 18 A, the current density in the active area becomes 200 A/cm², which indicates that the performance of the SI thyristor is superior to that of conventional IGBTs and MOSFETs.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Preparation and electrical properties of 0.4Pb(Zn1/3Nb2/3)O3-0.6Pb(Zr0.4Ti0.6)O3 thin films by 2-step annealing method

Films of (1−x)Pb(Zn_1/3Nb_2/3)O₃-xPb(Zr_0.4Ti_0.6) O₃ (x = 0.6, 40PZN-60PZT) were deposited on Pt/TiO₂/ SiO₂/Si substrate through spin coating. Using a combination of homogeneous precursor solution preparation and two-step pyrolysis process, we were able to obtain the 40PZN-60PZT thin films of perovskite phase virtually without pyrochlore phase precipitation after annealing above 650^∘C. But since annealing done at the high temperatures for extended time can cause diffusion of Pt, TiO₂ and Si, and precipitation of nonstoichiometric PbO, we adopted 2-step annealing method to circumvent these problems. The 2-step annealed films show dense microstructure than the 1-step films annealed at higher temperature. Furthermore, the root-mean-square surface roughness of 220 nm thick films which are annealed at 720^∘C for 1 min and then annealed at 650^∘C for 5 min was found to be 3.9 nm by atomic force microscopy as compared to the 12 nm surface roughness of the film annealed only at 720^∘C for 5 min. The electrical properties of 2-step annealed films are virtually same and those of the 1-step annealed films annealed at high temperature. The film 2-step annealed at 720^∘C for brief 1 min and with subsequent annealing at 650^∘C for 5 min showed a saturated hysteresis loop at an applied voltage of 5 V with remanent polarization (P _r) and coercive voltage (V _c) of 25.3 μC/cm² and 0.66 V respectively. The leakage current density was lower than 10⁻⁵A/cm² at an applied voltage of 5 V.     

Data analysis for dynamic contrast-enhanced MRI-based cerebral perfusion measurements: correcting for changing cortical CSF volumes

The time evolution of the histogram (number of pixels versus signal intensity) is used to calculate ΔR ₂ parameters from dynamic contrast-enhanced magnetic resonance (MR) imaging of the brain. This method partially corrects for partial volume effects and is an improvement over the approach using the signal intensity as a function of time when confounding factors such as changing cortical cerebrospinal fluid volumes are involved. The maximum value for ΔR ₂ is found to correlate with relative cerebral blood flow as assessed by xenon inhalation and can be used to discriminate between vascular dementia and healthy volunteers. With this method, the normal range for ΔR ₂ values is found to be the same for both young (19–40 years old) and elderly (65–85 years old) healthy volunteers.     

Numerical simulation of small silicon partially insulated MOSFETs

The scaling of conventional MOS bulk transistors with gate lengths below 100 nm seems to be difficult due to short channel effects. Especially the adjustment of the threshold voltage V _th is difficult because of the rapid drop down at shorter gate lengths. For low power consumption and high speed applications SOI technologies have been developed, but floating body effects, increasing leakage currents, kink phenomena and decreased heat dissipation occur in SOI-FETs. To combine the benefits of conventional and SOI-MOSFETs and to avoid the disadvantages, partially insulated FETs (Pi-FETs) with oxide regions under source and drain are candidates for scaling down the gate length into the deep submicron area [1–3, 5, 6]. We present the results of several numerical simulations to compare conventional bulk transistors, SOI-FETs and Pi-FETs in their static and dynamic behaviour.     

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the I_ON/I_OFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, S_Vth (the V_th sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a S_Vth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

     

Output characteristics model for an a‐Si ISFET pH sensor

A mathematical model for the calculation of the output characteristics of amorphous silicon hydrogenated (a‐Si:H) ion‐sensitive field‐effect transistors (ISFET) is developed, which depends on the integration of the conductivity channel versus gate voltage curve at fixed drain voltage. Single curve integration was changed to integration with many simple lines to obtain the I_D − V_D characteristics using computer programming. The results of this model were tested with those of experiments. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.