Low voltage analog circuit design techniques

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits     

SDW MOSFETs in LSI analog circuit design

Single-device-well (SDW) MOSFETs are based on merging two devices-a surface and a buried MOSFET to share the same device well and the same gate. They offer flexible circuit structures in the design of LSI analog circuit blocks with a circuit area saving which ranges typically from 30-60 percent. The authors discuss in detail the design and the analysis of SDW source followers and difference stages. It also gives examples of SDW circuit configurations for current sources, potential dividers, and output stages.     

Small-signal MOSFET models for analog circuit design

Presents first-order large-signal MOSFET models and derives corresponding small-signal models. The parameters of the small-signal models are related to operating-point bias and to the parameters of the IC process used to fabricate the device. The impact upon small-signal performance of many second-order effects present in small-geometry MOSFETs is explored. A representative analog circuit, fabricated with a 1 /spl mu/m feature-size NMOS technology, is analyzed using the small-signal models derived. Results of approximate analysis, without the use of computer aids, are compared with detailed computer simulation results.     

ADOPT-a CAD tool for analog circuit design

The structure and use of the ADOPT (Analog Design via Optimization) system are described. The ADOPT system consists of the circuit-simulation program SPICE, the nonlinear optimization program SUXES (Stanford University extractor of model parameters), and an interface subroutine called OPTLINK to link the two programs. The design of a third-order low-pass filter made up of seven transconductance elements is given as an example     

An MOS transistor model for analog circuit design

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model     

CCD低噪声读出电路设计

以红外增强型图像传感器TH7888A所得的微弱电压信号为输入,对图像传感器的模拟前端处理电路进行设计。采用巴特沃斯低通滤波器和全差分双相关采样的方法,提高整体电路的信噪比为67 dB,从而减少了后续电路的输入噪声。使用Proteus对所设计的低噪声、高增益放大电路的功能和噪声分析等特性进行全面的实验。实验结果表明,该设计能有效放大微弱电压信号,并可以对放大的电压信号进行准确的相关双采样去除KTC噪声、复位噪声。最后,在实际应用中,使用FPGA为硬件设计载体,以vivado作为软件开发环境,使用Verilog语言对时序发生器进行了硬件描述。FPGA生成的模拟信号分别作为读出电路的输入和采样的触发信号,并验证了其正确性和可行性。     

A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

State of the art in the analog CMOS circuit design

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

符号化仿真技术用于提高模拟集成电路设计良率

模拟电路对于工艺偏移的敏感性以及设计良率是模拟电路设计师关心的重要问题.由于数值仿真工具的局限性,至今设计界仍缺乏能有效提高电路可靠性与良率的通用设计辅助工具.提出利用符号化仿真器GRASS(Graph Reduction Analog Symbolic Simulator)快速导出频域设计指标关于电路参数的解析表示,并由此用三维立体图示的方式展示设计指标关于电路参数的依赖敏感度,设计者能够直观的判断如何选择合适的参数组合,以降低工艺偏移可能导致的电路性能恶化,从而提高设计良率.实验表明本文提出的方法可以有效地辅助设计者对于电路参数进行准确判断与选择,是一种值得在实际模拟电路设计中使用的辅助方法.     

Kink-free SOI analog circuit design with floating-body/NFD MOSFETs

A novel design approach to ensure general kink-free operation of floating-body/nonfully depleted (NFD) SOI analog circuits is described. The approach involves optimization of the bias and aspect ratios of all transistors that determine gain and current in a circuit such that they operate only in their kink-free voltage windows. The approach is demonstrated via a simulation-based design of the current cells of a 10-b floating-body/NFD DAC that shows good linearity and resolution at dc and frequencies up to 1 GHz. In contrast, the floating-body/NFD DAC without proper optimization shows poor and prohibitive performance     

The design of low-noise amplifiers

The essential theory and practical considerations for the design of low-noise amplifiers are gathered and organized to a uniform presentation. The relevant material is quite simple and straightforward, hopefully bringing within the reach of the interested circuit designer the "art" of low-noise-amplifier design.     

模拟电路符号化主极点分析与应用

模拟电路的主极点可以用于刻画系统带宽等电路行为,是模拟电路设计者关心的一个重要设计指标.利用主极点的符号化描述可以快速改变电路参数,以达到优化电路性能的目的,这是传统数值仿真器(如Spice)难以做到的.提出了一种主极点及其敏感度的符号化计算方法,并给出了一个应用例子,实验表明这个新的算法大大提高了模拟电路设计中主极点设计与优化的自动化程度,实验结果正确可靠.     

Rapid yield estimation as a computer aid for analog circuit design

A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulations, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage operational amplifiers and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield is presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer     

CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.     

基于方程和遗传算法的CMOS模拟单元电路优化

本文在CMOS单元电路优化中采用一种基于方程和遗传算法的优化方法.其采用描述电路行为的性能解析方程和遗传算法实现电路性能指标的优化.仿真结果表明,这种方法可以得到满意的仿真结果,同时所需的优化时间较短.     

C波段低噪声放大器的仿真设计

基于使LNA在5.5G~6.5G Hz频段内具有优良性能的目的,本设计中采用了具有低噪声、较高关联增益、PHEMT技术设计的ATF-35176晶体管,电路采用二级级联放大的结构形式,利用微带电路实现输入输出和级间匹配,通过ADS软件提供的功能模块和优化环境对电路增益、噪声系数、驻波比、稳定系数等特性进行了研究设计,最终...