A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm². The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2⁷-1 PRBS. The measured bit error rate for a 10 Gb/s 2⁷-1PRBS is less than 10^-12.     

High-Performance Optical 3R Regeneration for Scalable Fiber Transmission System Applications

This paper proposes and demonstrates optical 3R regeneration techniques for high-performance and scalable 10-Gb/s transmission systems. The 3R structures rely on monolithically integrated all-active semiconductor optical amplifier-based Mach-Zehnder interferometers (SOA-MZIs) for signal reshaping and optical narrowband filtering using a Fabry-Peacuterot filter (FPF) for all-optical clock recovery. The experimental results indicate very stable operation and superior cascadability of the proposed optical 3R structure, allowing error-free and low-penalty 10-Gb/s [pseudorandom bit sequence (PRBS) 2²³-1 ] return-to-zero (RZ) transmission through a record distance of 1 250 000 km using 10 000 optical 3R stages. Clock-enhancement techniques using a SOA-MZI are then proposed to accommodate the clock performance degradations that arise from dispersion uncompensated transmission. Leveraging such clock-enhancement techniques, we experimentally demonstrate error-free 125 000-km RZ dispersion uncompensated transmission at 10 Gb/s (PRBS 2²³-1) using 1000 stages of optical 3R regenerators spaced by 125-km large-effective-area fiber spans. To evaluate the proposed optical 3R structures in a relatively realistic environment and to investigate the tradeoff between the cascadability and the spacing of the optical 3R, a fiber recirculation loop is set up with 264- and 462-km deployed fiber. The field-trial experiment achieves error-free 10-Gb/s RZ transmission using PRBS 2²³-1 through 264 000-km deployed fiber across 1000 stages of optical 3R regenerators spaced by 264-km spans     

Optical phase-locked PSK heterodyne experiment at 4 Gb/s

A 4 Gb/s phase-locked optical PSK (phase shift keying) heterodyne communication system is demonstrated. The receiver was implemented with a single 100-Ω loaded p-i-n photodiode and a 1320-nm diode-pumped miniature Nd:YAG laser as a local oscillator. For a 2⁷-1 PRBS (pseudorandom bit sequence), the receiver sensitivity was -34.2 dBm or 631 photons/bit. The corresponding power on the surface of the detector was -37.3 dBm or 309 photons/bit. With a 2¹⁵-1 PRBS, a 2.6 dB additional sensitivity degradation was observed due to the nonideal frequency response of the phase modulator and the receiver amplifiers     

One-third terabit/s transmission through 150 km ofdispersion-managed fiber

340 Gb/s (seventeen 20-Gb/s 2³¹-1 PRBS NRZ channels) were transmitted through 150 km of fiber with 50 km amplifier spacing. Chromatic dispersion penalties and four-photon mixing effects were minimized by dispersion management     

A Si bipolar phase and frequency detector IC for clock extractionup to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >±100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2²³-1. A 0.9-μm 12-GHz f_T silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W     

A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

We present a pseudorandom bit sequence (PRBS) generator that outputs a 2⁷-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

A packaged broad-band monolithic variable gain amplifierimplemented in AlGaAs/GaAs HBT technology

Broad-band amplifiers find application in fiber-optic communication link and instrumentation or serve as generic components in high-speed electronic test laboratories. With an advanced AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology, we have designed and fabricated broad-band monolithic variable gain amplifiers (VGAs). High-speed packages for the VGAs were carefully designed to minimize insertion and return losses and to suppress undesired package cavity resonances. Accurate and efficient models for the packages were obtained based on experimental data so that their parasitic effects could be considered in the VGA design. The packaged VGAs provided 10-16 dB adjustable gain with approximately ±1 dB gain variations and constant group delay in the DC-26 GHz band, and showed better than 10 dB input/output return losses in the amplifier passband. When the packaged VGAs were inserted in a 30 Gb/s electronic link, error-free operation was achieved for a 2³¹-1 input pseudorandom bit sequence. These VGAs can be used in fiber-optic transmission systems with data rates up to 30 Gb/s     

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10^-12 with 2³¹-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply     

Numerical study of moderate distance high bit-ratealternating-amplitude soliton systems

We present a numerical investigation of alternating-amplitude soliton systems. We propagate 100 Gb/s, pseudorandom bit sequences of 2 ⁵-1 to 2⁷-1 solitons through fibers of different lengths and calculate the corresponding eye opening penalty at the receiver. The influence of different amplitude ratios, amplifier spacings, pulse widths, and dispersion slopes as well as of the soliton self-frequency shift are studied. We also study the effect of compression of the alternative-amplitude solitons with the larger amplitudes to preserve their soliton character and the impact of the relative initial phase between the alternating-amplitude solitons. When the amplifier spacing is 10 km the system length can be at least 400 km with alternating-amplitude solitons compared to only 200 km in the case of equal amplitude solitons with similar penalties. Our simulations show-that third-order dispersion and the soliton self-frequency shift limit the maximum allowable amplitude ratio     

1 Gbit/s PSK homodyne transmission system using phase-lockedsemiconductor lasers

Homodyne detection of 1 Gb/s pilot-carrier (BPSK) optical signals using phase-locked 1.5 μm external-cavity semiconductor lasers is discussed. After 209 km fiber transmission of a 2¹⁵-1 pseudorandom binary sequence (PRBS), the measured receiver sensitivity is 52.2 dBm or 46 photons/bit. Experimental evidence of the data-to-phase-lock crosstalk that potentially limits the usable ratio of linewidth to bit rate in pilot-carrier PSK homodyne systems is presented     

Penalty-free error-free all-optical data pulse regeneration at 84Gb/s by using a symmetric-Mach-Zehnder-type semiconductor regenerator

Penalty-free data-pulse regeneration at 84 Gb/s was achieved down to an error rate level of 1×10^-11 by using a data pattern length of 2³¹-1. A symmetric-Mach-Zehnder-type all-optical polarization-insensitive semiconductor regenerator was used     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

An ultra-low-power, 2$ ^7-$1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz$f_T$SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.     

16 Gbit/s transmission experiments using a directly modulated 1.3μm DFB laser

A 16 Gb/s electrically time-division-multiplexed lightwave link is discussed. The 16 Gb/s electronic signal was generated by multiplexing together eight copies of the 2-Gb/s pseudorandom sequence (length 2¹⁵-1) produced by a commercial BER test set. A 22-km transmission distance was achieved using a directly modulated, 1.3-μm wavelength DFB laser and a 50-Ω p-i-n receiver. Receiver sensitivity for a BER of 10^-9 was -2.0 dBm. The addition of an optical preamplifier required a more sensitive receiver to avoid saturation-induced distortion in the preamplifier. This was accomplished by reducing the 2-Gb/s word length to 24 b, thereby lowering the intersymbol interference penalty and effectively increasing the receiver sensitivity. Under these conditions, the optical preamplifier receiver sensitivity was -19 dBm, and a 64.5-km transmission was demonstrated     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

A monolithic 156 Mb/s clock and data recovery PLL circuit using thesample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2²³-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor     

PSK optical homodyne detection using external cavity laser diodesin Costas loop

5-Gb/s optical PSK (phase-shift keying) homodyne detection experiments are discussed. In these experiments, the optical carrier is recovered by a Costas optical phase-locked loop using a multielectrode local oscillator (DFB) laser diode at 1.55 μm with a flat FM response. Although the beat linewidth of 80 kHz is broad compared to the loops in other phase-locked loop (PLL) experiments, phase locking with Costas loop is confirmed at 5 Gb/s by increasing the loop natural frequency. The receiver sensitivity is -42.2 dBm or 93 photon/bit for a 2⁷-1 pseudorandom bit sequence (PRBS) in front of a 90° hydride     

Design, modeling, and characterization of monolithically integratedInP-based (1.55 μm) high-speed (24 Gb/s) p-i-n/HBT front-endphotoreceivers

High-speed, long-wavelength InAlAs/InGaAs OEIC photoreceivers based on a p-i-n/HBT shared layer integration scheme have been designed, fabricated and characterized. The p-i-n photodiodes, formed with the 6000 Å-thick InGaAs precollector layer of the HBT as the absorbing layer, exhibited a responsivity of ~0.4 A/W and a -3 dB optical bandwidth larger than 20 GHz at λ=1.55 μm. The fabricated three-stage transimpedance amplifier with a feedback resistor of 550 Ω demonstrated a transimpedance gain of 46 dBΩ and a -3 dB bandwidth of 20 GHz. The monolithically integrated photoreceiver with a 83 μm p-i-n photodiode consumed a small dc power of 35 mW and demonstrated a measured -3 dB optical bandwidth of 19.5 GHz, which is the highest reported to date for an InAlAs/InGaAs integrated front-end photoreceiver. The OEIC photoreceiver also has a measured input optical dynamic range of 20 dB. The performance of individual devices and integrated circuits was also investigated through detailed CAD-based analysis and characterization. Transient simulations, based on a HSPICE circuit model and previous measurements of eye diagrams for a NRZ 2³¹-1 pseudorandom binary sequence (PRBS), show that the OEIC photoreceiver is capable of operation up to 24 Gb/s