New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.     

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer

900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.     

A modified autocorrelation method of linear prediction for pitch-synchronous analysis of voiced speech

A modified autocorrelation method of linear prediction is proposed for pitch-synchronous analysis of voiced speech. The method needs one full period of speech data for analysis and assumes periodic extension of the data. This method guarantees the stability of the estimated all-pole filter and is shown to perform better than the covariance and autocorrelation methods of linear prediction.     

A 6-7 GHz, 40 dB receiver RF front-end with 4.5 dB minimum noise figure in 0.13μm CMOS for IR-UWB applications

A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP₃ of-11 dBm.The core receiver （without test buffer） consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm² area.