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1.
A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm2, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10-6, with random data input of length 223-1. The power dissipation is 72 mW from a 2.5-V supply 相似文献
2.
Lao Z.H. Langmann U. Albers J.N. Schlag E. Clawin D. 《Solid-State Circuits, IEEE Journal of》1995,30(2):129-132
The 4:1-multiplexer reported here is based on a 21 GHz fT 0.4 μm silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V 相似文献
3.
《Solid-State Circuits, IEEE Journal of》2009,44(5):1391-1400
4.
A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm2. It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW 相似文献
5.
Rennie D. Sachdev M. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):796-803
This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 27 - 1 calibration improved the measured bit error rate from 4.6 x 10-2 to less than 10-13. 相似文献
6.
Yamaguchi K. Fukaishi M. Sakamoto T. Akiyama N. Nakamura K. 《Solid-State Circuits, IEEE Journal of》2001,36(11):1666-1672
An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm2. It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5 相似文献
7.
Inhwa Jung Gunok Jung Janghoon Song Moo-Young Kim Junyoung Park Sung Bae Park Chulwoo Kim 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(2):116-120
Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mum CMOS technology occupies only 0.004 mm 2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a plusmn 2% phase error having one-cycle lock time. 相似文献
8.
Zhihao Lao Langmann U. Albers J.N. Schlag E. Clawin D. 《Solid-State Circuits, IEEE Journal of》1996,31(1):54-60
A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f T 0.4 μm Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of ⩾250°. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer IC's at 10 Gb/s 相似文献
9.
Bastiaansen C.A.A. Groeneveld D.W.J. Schouwenaars H.J. Termeer H.A.H. 《Solid-State Circuits, IEEE Journal of》1991,26(7):917-921
A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-μm double-metal CMOS technology and the chip area is 0.4 mm2. This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches 相似文献
10.
Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques
New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μAp-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm2 and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits 相似文献
11.
A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision-directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm2 in a 1.2-μm CMOS process. At 180 Mb/s, the rms clock fitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors 相似文献
12.
A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 231-1 PRBS data signal at 43 Gbit/s 相似文献
13.
《Solid-State Circuits, IEEE Journal of》2008,43(8):1763-1771
14.
《Solid-State Circuits, IEEE Journal of》2009,44(11):2901-2910
15.
Jankovic M. Breitbarth J. Brannon A. Popovic Z. 《Microwave Theory and Techniques》2008,56(7):1511-1515
16.
Byun S. Lee J.C. Shim J.H. Kim K. Yu H.-K. 《Solid-State Circuits, IEEE Journal of》2006,41(11):2566-2576
This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 231-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s 相似文献
17.
Wennekers P. Novotny U. Huelsmann A. Kaufel G. Koehler K. Raynor B. Schneider J. 《Solid-State Circuits, IEEE Journal of》1992,27(10):1347-1352
A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V 相似文献
18.
The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 223-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor 相似文献
19.
Youngkou Lee Sungsoo Choi Seung-Geun Kim Jeong-A Lee Kiseon Kim 《Electronics letters》1999,35(24):2073-2074
The authors propose and evaluate the performance of a 2N times clock multiplier that controls memory components for high-speed data communications. To improve the reliability of the circuit, a symmetric circuit structure is used, while to verify circuit operation by means of a simple method, an MVU estimator is found from simulation data. The proposed circuit can provide clock rates, which are usually required in the multiple phase shift keying (MPSK) or multiple quadrature amplitude modulation (MQAM) modulation schemes, of 2 to 2N times that of the input clock 相似文献
20.
A clock recovery IC for optical fibre communication at multigigabit/s is proposed. The clock frequency extracted corresponds to half the bit rate. The 2:1 frequency division is carried out by a double balanced mixer and the frequency selection by an SAW filter. Circuit simulations are based on a standard 2 ?m silicon bipolar technology. The circuit was optimisd at 3.4 Gbit/s for a power consumption of 220 mW with a 1.7 GHz SAW filter (Q = 340). The dynamic clock phase jitter, estimated from circuit simulations, is less than 0.5°. Circuit simulations predict that the operating bit rate may be exended up to 4.5 Gbit/s. 相似文献