Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

This paper proposes an oxide TFT DC-type shift register that consists of eleven TFTs and one bootstrapping capacitor. The proposed circuit connects drain nodes of large size pull-up TFTs of output drivers to positive supply voltage instead of alternating clock signals for low power consumption. In addition, a robust internal inverter capable of maintaining the high voltage level of the output over the large positive threshold voltage shift by bootstrapping is implemented. For a 120 Hz Full-HD display, the SPICE simulation estimates the clock power consumption of the proposed DC-type circuit as 0.56 mW at 32 shift registers and ensures the robust operation over the wide range of threshold voltage shift from −4 V to 10 V.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel have been developed. The data drivers include shift registers, sample‐and‐hold circuits, and operational amplifiers, and drive LCD panels using a line‐at‐a‐time addressing method. To reduce the power consumption of the shift register, a dot‐clock control circuit has been developed. Using this circuit, the power consumption of the shift register has been reduced to 36% of that of conventional circuits. To cancel the offset voltage generated by the operational amplifier, an offset cancellation circuit for low‐temperature poly‐Si TFTs has been developed. This circuit is also able to avoid any unstable operation of the operational amplifier. Using this circuit, the offset voltage has been reduced to one‐third of the value without using the offset cancellation circuit. These data drivers have been connected to an LCD panel and have realized an SVGA display on a 12.1‐in. a‐Si TFT‐LCD panel.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

采用脉冲供电的催化传感器的工作性能研究

针对煤矿瓦斯监测系统中催化传感器功耗高的问题,提出了采用脉冲供电方式对传统供电方式进行改进的方法.分析了载体催化元件的工作特性和脉冲供电原理;通过实验研究了不同CH4浓度的标准气样下,供电脉冲频率、脉宽（即占空比）与传感器灵敏度之间的关系.实验结果表明：和普通催化传感器相比,采用脉冲供电的将会很大程度上降低催化传感器的功耗,延长便携式设备的生命周期;同时,分析得到采用脉冲供电的可行性和最佳频率.     

Modified dynamic current mode logic based LFSR for low power applications

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz.     

高精度连续可调高压开关电源的设计

提出了一种高精度连续可调的高压开关电源设计方案。电源采用基于SG3525的恒频脉宽调制技术,通过单片机控制可控增益放大器实现输出电压的连续调整,该电源具有高电压输出精度高、连续可调、功耗小等特点。实验结果表明,当该电源输出电压由1kV-25kV可调输出时,输出电压误差最大为1．6％。     

Register spilling via transformed interference equations for PAC DSP architecture

Digital signal processors (DSPs) with very long instruction word (VLIW) data‐path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multibank register architectures are being adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. This paper addresses the issues of reducing the spill code for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register‐file architecture provides the opportunity to spill‐out register values onto different register banks. We present a conceptual framework based on the universal and the proxy interference graphs to model the live ranges of registers for spilling codes to different register banks. Heuristic algorithms are then developed on the basis of this concept. By heuristically estimating the register pressure for each register file, we treat different register banks as optional spilling locations in addition to traditional spilling to memory. Experiments were performed on the parallel architecture core VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64‐based compiler. The experimental results show that our approach can improve the performances on average for DSPStone and MiBench benchmarks with spilling cases by 7.1% and 21.6%, respectively, compared with the one always handling spill code in memory. Copyright © 2013 John Wiley & Sons, Ltd.     

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file.We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine.     

基于单片机控制的单相变三相稳压电源研究

本文研究在单相供电条件下,如何设计简易高效的三相稳压电源,为小功率电动机供电,用三相电机取代单相电机,以提高在小功率范围内驱动电动机的机械效率和运行平稳性,从而达到高效、节能、降噪和环保的目的。该方案中采用了基于单片机控制的数控移相、过零比较、相位检测、脉宽调制和滤波等技术。采用PROTEUS软件对所设计的单相转三相变...     

基于钟控非线性序列的RFID伪随机数发生器设计

以RFID加密系统的伪随机数发生器为研究对象,提出以线性反馈移位寄存器（LFSR）为基本部件的复合型钟控非线性伪随机数发生器的设计方法。通过Matlab和QuartusII对该设计的周期、线性复杂度、均匀性、功耗等特征参数进行分析,最后硬件电路采用FPGA产品中低成本、低功耗的Cyclone Ⅱ实现。此设计既保持了基本钟控非线性序列循环周期长、线性复杂度高的特性,同时提高了输出序列取值分布的均匀性,电路结构简单,并行输出16位数据,能够满足RFID加密系统的要求。     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

Register port complexity reduction in wide-issue processors with selective instruction execution

As the width of the processor grows, complexity of a register file (RF) with multiple ports grows more than linearly and leads to larger register access time and higher power consumption. Analysis of SPEC2000 programs reveals that only a small portion of the instructions in a program (16% in integer and 38% in floating-point) require both the source operands. Also, when the programs are executed in an 8-wide processor only a very few (two or less) two-source instructions are executed in a cycle for a significant portion of time (more than 98% for integer and 93% for floating-point), leading to a significant under-utilization of register port bandwidth. In this paper, we propose a novel technique to significantly reduce the number of register ports, with a very minor modification in the select logic to issue only a limited number of two-source instructions each cycle. This is achieved with no significant impact on processor’s overall performance. The novelty of the technique is that it is easy to implement and succeeds in reducing the access time, power, and area of the register file, without aggravating these factors in any other logic on the chip. With this technique in an 8-wide processor, as compared to a conventional 128-entry RF with 16 read ports, for integer programs a register file can be designed with 11 or 10 read ports as these configurations result in instructions per cycle (IPC) degradation of only 0.929% and 3.38%, respectively. This significantly low degradation in IPC is achieved while reducing the register access time by 9% and 12%, respectively, and reducing power by 35% and 50%, respectively. For FP programs, a register file can be designed with 12 read ports (1.16% IPC loss, 8% less access time, and 28% less power) or with 11 read ports (3.5% IPC loss, 9% less access time, and 35% less power). The paper analyzes the performance of all the possible flavors of the proposed technique for register file in both 4-wide and 8-wide processors, and presents a choice of the performance and register port complexity combination to the designer.     

A 200 W broadband high power amplifier using hybrid power combining network and digital level control

In this article, a 2 to 6 GHz solid‐state power amplifier with 53 dBm output power has been analyzed, designed, and fabricated. To achieve a wideband high output power, we introduce a 16‐way hybrid power combiner based on microstrip planar binary and parallel structures. The simulation and measurement results of the proposed hybrid power combining network (PCN) show that the maximum power combining efficiency is around 86% with the insertion loss of around 0.6 to 1.5 dB and an isolation of 20 dB between the ports. Also, to compensate the output power variations due to the thermal and operating frequency changes across the bandwidth, a digital level control (DLC) unit utilizing an agile control algorithm is proposed which decreases the output power variations to 2% of the desired output power. A cooling heatsink fan system has been also designed in order to transfer the heat generated power to the air. The measured output power for the applied input continuous wave is higher than 52.5 dBm. In addition, the power added efficiency (PAE) is better than 15% across the wide portion of the bandwidth and the measured third‐order intermodulation is about 20 dBc (average).     

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

An intra‐panel interface addressing all of the high‐speed, low‐power, and low‐electromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4‐Gbps data‐rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power‐saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin‐film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65‐nm and 180‐nm complementary metal‐oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band‐20 and GSM 850 bands. The proposed power‐saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced‐voltage differential signaling interface circuit.     

双级矩阵变换器空间矢量调制策略改进

针对双级矩阵变换器空间矢量脉宽调制策略存在控制复杂度高、不能对双级矩阵变换器的输入功率因数进行调节的问题,提出了采用间接空间矢量调制策略的方案:①各PWM周期内直流平均电压为一恒定值,从而免去了逆变级调制系数的修正;②输入功率因数角可调。同时,利用参考电压和变换矩阵对该调制策略进行简化,使其能够更有效地控制无功功率和输出电压。仿真结果验证了该调制策略的正确性和有效性。     

Performance Enhancement of PV Based Boost Cascaded Fifteen Level Inverter for AC Loads

In this research work, single-stage fifteen levels cascaded DC-interface converter (CDDCLC) is proposed for sun arranged photovoltaic technology (PV) applications. The proposed geography is joined with help DC chopper and H-associate inverter to upgrade the power converter to accomplish the diminished harmonic profile. In assessment with the customary inverter structures, the proposed system is used with diminished voltage stress, decreased switch count and DC source tally. The proposed research work with cascaded DC link converter design requires three DC sources for combining fifteen-level AC output. This investigation structure switching technique is phase opposition and disposition pulse width modulation technique (POPD) which results in improved quality of obtained output AC power with 6.73% THD and also determinedly recommended for power converters used in UPS and drive applications since it is extremely affordable. A simulation and prototype model of fifteen-level CDDCLC system is deployed and its performance is analyzed for various operating conditions.     

智能振动时效控制系统PWM设计

分析了智能振动时效控制系统在实现脉冲宽度调制时存在的单片机定时器定时时间过短、定时器初始值的写入方法、频率精度低等问题,给出了相应的解决方法;提出了利用单片机实现脉冲宽度调制的基本思路:定时器在高电平和低电平时分别定时,使单片机通用I/O口输出频率不变或频率可变而宽度不变的脉冲。Proteus与Keil C联合仿真结果表明,智能振动时效控制系统脉冲宽度调制设计方法能够输出符合要求的脉冲信号。     

2kV高稳定度高压脉冲电源设计

在一些光学精密仪器的应用场合中,不仅需要脉冲电源在时间上能够提供精确的控制,而且需要具有高稳定度的输出,以提高光电系统的探测性能;运用基于高压开关的两级式方法,采用单级高功率MOSFET开关结合具有高稳定输出的直流电源的结构,设计了输出辐度可达2kV的高稳定负脉冲电源;测试结果表明,在输出脉冲宽度为8 μs时,脉冲前沿约为48 ns,系统延迟时间约为140 ns,负脉冲超调参数约为1%。该系统具有结构简单、可靠性高、高稳定性输出等优点,可以为特定的光电器件提供优质的控制方式。     

Evaluation of single‐, pre‐emphasis,and dual‐driving methods in large‐sized TFT‐LCDs

Abstract— As the panel size and the frame frequency of TFT‐LCDs increases, driving issues become much more important for larger‐sized and higher‐resolution TFT‐LCDs. In our previous paper, the pre‐emphasis driving method was proposed to shorten the driving time of the data line with heavy loads of the large‐sized TFT‐LCDs. This paper proposes a simulation model based on the evaluation results of the developed pre‐emphasis source driver, and the issues of driving the data line with heavy loads are reviewed. The single‐, pre‐emphasis, and dual‐driving methods are compared in terms of their driving time and power consumption for large‐sized TFT‐LCDs with various resistances and capacitances of the data lines. At a panel load of 250‐pF capacitance and 15‐kΩ resistance in full‐HD resolution, the pre‐emphasis driving can reduce the pixel driving time to 66% with a 54% increase in the analog power consumption.