Role of tunneling layer in graphene-oxide based organic nonvolatile memory transistors

This paper demonstrates non-volatile memory transistor using solution processable graphene oxide (GO) as charge storage nodes in the configuration, p⁺⁺Si/SiO₂/GO/Tunneling layer/Pentacene/Au. The tunneling layers are polymethylmethacrylate (PMMA) and polyvinylphenol (PVP). GO film could be deposited as single layered flakes with a uniform distribution using spin coating technique. The devices with PMMA as charge tunneling layer exhibited higher mobility and on/off ratio than PVP based devices. The devices show a large positive threshold voltage shift (∼24 V for PMMA and ∼15 V for PVP) from initial value during programming at gate voltage of +80 V kept for 10 s. The transfer curves can be restored approximately to its initial condition by applying an erasing voltage of −30 V for 10 s for both the devices. Since such a large shift is not observed without GO layer, we consider that memory effect was due to electron trapping in GO. Further, retention of the initial memory window was measured to be 63% and 37% after 3000 s for PMMA and PVP based devices, respectively.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm²/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10⁴. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.     

Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

The influence of visible light on the gate bias instability of In-Ga-Zn-O thin film transistors

We investigated the effect of photon irradiation with various energies on the gate bias instability of indium-gallium-zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (V_th) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the V_th value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative V_th shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.     

Lowering programmed voltage of organic memory transistors based on polymer gate electrets through heterojunction fabrication

The authors report on low operation voltage memory cells based on heterojunction ambipolar organic transistors with polymer gate electret (PGE). The introduction of the N,N′-dioctyl perylene diimide/pentacene heterojunction into the memory OFETs with PGE successfully lowered the memory cells’ reading, writing and erasing programmed voltages (reading voltage of 2 V, writing and erasing programmed voltages of 10 V). Meanwhile, the memory devices showed reproducible and durable memory behavior in more than 500 cycles’ testing. The built-in electric field-effect at heterojunction surface should efficiently reduce operation voltage of the memory devices.     

Acrylate-based nanocomposite zirconium-dispersed polymer dielectric for flexible oxide thin-film transistors with a curvature radius of 2 mm

Novel hybrid dielectric film is synthesized at a low temperature of 150 °C using a solution process. Zirconium acrylate (ZrA) and poly(methyl methacrylate) (PMMA) comprise the inorganic and organic components, respectively. The acrylate-based molecular structure of both ingredients allows the facile formation of hybrid ZrA/PMMA dielectric film with neither additional coupling agent nor ultraviolet photon irradiation. The high quality of the hybrid ZrA/PMMA dielectric film is confirmed by its high dielectric constant of 5.5 and low leakage current density of 1.7 × 10⁻⁸ A/cm² at the electric field of 1 MV/cm. The indium gallium tin oxide (IGTO) transistors with the optimal ZrA/PMMA gate insulator layer are fabricated on the polyimide substrate at the maximum high temperature of 150 °C. They exhibit hysteresis-free high performance with high carrier mobility of 24.3 cm²V⁻¹s⁻¹, gate swing of 0.61 V/decade and I_ON/OFF ratio of 4 × 10⁶. Owing to the intrinsic deformability of hybrid dielectric film, these transistors maintained electrical performance after 100 cycles of mechanical bending to the extremely small radius of curvature of 2 mm.     

High performance p-type organic thin film transistors with an intrinsically photopatternable,ultrathin polymer dielectric layer

A high-performing bottom-gate top-contact pentacene-based oTFT technology with an ultrathin (25–48 nm) and electrically dense photopatternable polymeric gate dielectric layer is reported. The photosensitive polymer poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) is patterned directly by UV-exposure (λ = 254 nm) at a dose typical for conventionally used negative photoresists without the need for any additional photoinitiator. The polymer itself undergoes a photo-Fries rearrangement reaction under UV illumination, which is accompanied by a selective cross-linking of the macromolecules, leading to a change in solubility in organic solvents. This crosslinking reaction and the negative photoresist behavior are investigated by means of sol–gel analysis. The resulting transistors show a field-effect mobility up to 0.8 cm² V⁻¹ s⁻¹ at an operation voltage as low as −4.5 V. The ultra-low subthreshold swing in the order of 0.1 V dec⁻¹ as well as the completely hysteresis-free transistor characteristics are indicating a very low interface trap density. It can be shown that the device performance is completely stable upon UV-irradiation and development according to a very robust chemical rearrangement. The excellent interface properties, the high stability and the small thickness make the PNDPE gate dielectric a promising candidate for fast organic electronic circuits.     

High-mobility pentacene thin-film transistor by using LaxTa(1−x)Oy as gate dielectric

Pentacene organic thin-film transistors (OTFTs) using La_xTa_(1−x)O_y as gate dielectric with different La contents (x = 0.227, 0.562, 0.764, 0.883) have been fabricated and compared with those using Ta oxide or La oxide. The OTFT with La_0.764Ta_0.236O_y can achieve a carrier mobility of 1.21 cm² V⁻¹s⁻¹s, which is about 40 times and two times higher than those of the devices using Ta oxide and La oxide, respectively. As supported by XPS, AFM and noise measurement, the reasons lie in that La incorporation can suppress the formation of oxygen vacancies in Ta oxide, and Ta content can alleviate the hygroscopicity of La oxide, resulting in more passivated and smoother dielectric surface and thus larger pentacene grains, which lead to higher carrier mobility.     

Low-voltage p-channel, n-channel and ambipolar organic thin-film transistors based on an ultrathin inorganic/polymer hybrid gate dielectric layer

A key issue in research into organic thin-film transistors (OTFTs) is low-voltage operation. In this study, we fabricated low-voltage operating (below 3V) p-channel, n-channel and ambipolar OTFTs based on pentacene or/and C₆₀ as the active layers, respectively, with an ultrathin AlO_X/poly(methyl methacrylate co glycidyl methacrylate) (P(MMA–GMA)) hybrid layer as the gate dielectric. Benefited from the enhanced crystallinity of C₆₀ layer and greatly reduced density of electron trapping states at the interface of channel/dielectric due to the insertion of ultrathin pentacene layer between C₆₀ and P(MMA–GMA), high electron mobility can be achieved in present pentacene/C₆₀ heterostructure based ambipolar OTFTs. The effect of the thickness of pentacene layer and the deposition sequence of pentacene and C₆₀ on the device performance of OTFTs was studied. The highest electron mobility of 3.50 cm²/V s and hole mobility of 0.25 cm²/V s were achieved in the ambipolar OTFT with a pentacene (3.0 nm)/C₆₀ (30 nm) heterostructure.     

High performance,foldable, organic memories based on ultra-low voltage,thin film transistors

We report on the fabrication of highly flexible OTFT-based memory elements with excellent mechanical stability and high retention time. The devices have been fabricated using a combination of two ultrathin AlOx and Parylene C as dielectric, and TIPS-Pentacene as the semiconductor, obtaining high performing low voltage transistors with mobility up to 0.4 cm²/V s, and I_on/I_off ratio of 10⁵. Charge trapping in the Parylene C electret layer is the mechanism that allows employing these devices as non volatile memory elements, with retention time as high as 4 × 10⁵ s. The electromechanical characterization demonstrated that such memory elements can be cyclically bent around a cylinder with a radius of 150 μm without losing the stored data.     

High mobility multibit nonvolatile memory elements based organic field effect transistors with large hysteresis

High mobility multibit nonvolatile memory elements based on organic field effect transistors with a thin layer of polyquinoline (PQ) were reported. The devices show a high mobility of 1.5 cm² V⁻¹ s⁻¹ in the saturation region which is among the best reported for nonvolatile organic memory transistors. The multibit nonvolatile memory elements can be operated at voltage less than 100 V with good stability under continuous operation condition and show long retention time. The different initial scanning positive gate voltages to −100 V result in several ON states, while the scanning gate voltage from −100 V to positive voltage leads to same OFF state. The charge trapping model of electrons into the PQ layer was used to explain the origin of the memory properties.     

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

All solution-processed organic single-crystal transistors with high mobility and low-voltage operation

High-mobility organic single-crystal field-effect transistors of 3,11-didecyldinaphtho[2,3-d:2′,3′-d′]benzo[1,2-b:4,5-b′]-dithiophene (C₁₀-DNBDT) operating at low driving voltage are fabricated by an all-solution process. A field-effect mobility as high as 6.9 cm²/V s is achieved at a driving voltage below 5 V, a voltage as low as in battery-operated devices, for example. A low density of trap states is realized at the surface of the solution-processed organic single-crystal films, so that the typical subthreshold swing is less than 0.4 V/decade even on a reasonably thick amorphous polymer gate dielectrics with reliable insulation. The high carrier mobility and low interface trap density at the surface of the C₁₀-DNBDT crystals are both responsible for the development of the high-performance all-solution processed transistors.     

Electrical characteristics and reliability properties of metal-oxide-semiconductor capacitors with HfZrLaO gate dielectrics

Metal-oxide-semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high-κ gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density (J_g) is only 9.3 × 10⁻¹ A/cm². The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter (γ) and activation energy (ΔH₀) are determined around 5.9-7.0 cm/MV and 0.54-0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V.     

Downscaling of n-channel organic field-effect transistors with inkjet-printed electrodes

In this contribution we demonstrate for the first time a downscaled n-channel organic field-effect transistors based on N,N′-dialkylsubstituted-(1,7&1,6)-dicyanoperylene-3,4:9,10-bis(dicarboximide) with inkjet printed electrodes. First we demonstrate that the use of a high boiling point solvent is critical to achieve extended crystalline domains in spin-coated thin films and thus high electron mobility >0.1 cm² V⁻¹ s⁻¹ in top-gate devices. Then inkjet-printing is employed to realize sub-micrometer scale channels by dewetting of silver nanoparticles off a first patterned gold contact. By employing a 50 nm crosslinked fluoropolymer gate dielectric, ∼200 nm long channel transistors can achieve good current saturation when operated <5 V with good bias stress stability.     

Hydrated bovine serum albumin as the gate dielectric material for organic field-effect transistors

Bovine serum albumin (BSA) is a natural protein with good hydration ability which contains acidic and basic amino acid residues of ca. 34% in total. In vacuum, pentacene organic field-effect transistors (OFETs) with BSA as the gate dielectric exhibits a field-effect mobility value (μ_FE,sat) of 0.3 cm² V⁻¹ s⁻¹ in the saturation regime and a threshold voltage (V_TH) of ca. −16 V. BSA is easy to be hydrated in air ambient. Electrical properties of BSA in vacuum and hydrated BSA in air ambient are characterized. Similar to polyelectrolyte, hydrated BSA may act the gate dielectric with the formation of electric double-layer capacitors (EDLCs) to improve the device performance. In a relative humidity of 47%, the μ_FE,sat value increases to 4.7 cm² V⁻¹ s⁻¹ and the V_TH reduces to −0.7 V. Generation of mobile ions in hydrated BSA and the formation of EDLCs are discussed.     

High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack

Short channel p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with GdScO₃ gate dielectric were fabricated on a quantum well strained Si/strained Si_0.5Ge_0.5/strained Si heterostructure on insulator. Amorphous GdScO₃ layers with a dielectric constant of 24 show small hysteresis and low density of interface states. All devices show good performance with a threshold voltage of 0.585 V, commonly used for the present technology nodes, and high I_on/I_off current ratios. We confirm experimentally the theoretical predictions that the drive current and the transconductance of the biaxially strained (1 0 0) devices are weakly dependent on the channel orientation. The transistor’s hole mobility, extracted using split C-V method on long channel devices, indicates an enhancement of 90% (compared to SiO₂/SOI transistors) at low effective field, with a peak value of 265 cm²/V s. The enhancement is however, only 40% at high electrical fields. We demonstrate that the combination of GdScO₃ dielectric and strained SiGe layer is a promising solution for gate-first high mobility short channel p-MOSFETs.