A single-input dual-output 13.56 MHz CMOS AC–DC converter with comparator-driven rectifiers for implantable devices

A highly efficient single-input, dual-output AC–DC converter for wireless power transfer in implantable devices is implemented using the 0.18-µm CMOS process. The proposed AC–DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm².     

1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.     

Low-power organic field-effect transistors and complementary inverter based on low-temperature processed Al2O3 dielectric

Organic-based complementary inverter could be a key component in future flexible and portable electronic products, which require low-power operation, high operating stability and flexible compatibility at the same time. A simple method for making excellent Al₂O₃ gate dielectric is developed toward the target, and it is a low-cost solution process with a low annealing temperature compatible with plastic substrates. Utilizing the Al₂O₃ dielectric, both p-type and n-type low-voltage organic field-effect transistors (OFETs) are realized. The device operating voltage is down to ±3 V, and the On/Off ratio is up to 10⁶. The hole and electron field-effect mobilities are 2.7 cm²/V and 0.2 cm²/V, respectively, and the subthreshold swing is as small as about 110 mV/decade. The high quality of the Al₂O₃ dielectric results in high operating stability of the devices. The p-type and n-type OFETs are integrated to achieve a low-power complementary inverter with a large gain, which can be successfully fabricated on a flexible substrate.     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

High-frequency performances of a partially depleted 0.18-μmSOI/CMOS technology at low supply voltage-influence of parasiticelements

This paper shows for the first time the high-performances of a partially depleted 0.18-μ_m technology at low supply voltage. The SOI technology uses a standard digital process with a TiSi ₂ salicided polysilicon gate and a low dose SIMOX substrate. The process does not include any specific feature like T-gate, or high-resistivity SOI substrate. At 1 V, and 2 GHz the current gain and the unilateral power gain are higher than 15 dB for both 0.18 μm gate length NMOS and PMOS transistors. At 1.5 V, the 0.18-μm NMOS and PMOS show a transition frequency of, respectively, 51 GHz and 23 GHz and a maximum oscillation frequency of 28 GHz and 13 GHz. These results have been obtained with an optimized transistor geometry to reduce the influence of the access resistances. The high-frequency potential of this 0.18-μm SOI technology demonstrates the possible integration of microwave functions with digital circuits on a single chip for low-power, low-voltage applications like wireless telecommunication     

Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.     

Solution processed inverter based on zinc oxide nanoparticle thin-film transistors with poly(4-vinylphenol) gate dielectric

An enhancement-load inverter using bottom-gated ZnO nanoparticle thin-film transistors and a polymer gate dielectric is demonstrated. The deposition of the ZnO active layer is done by spin coating of a colloidal dispersion and is hence cost-effective. Since the maximum process temperature is 200 °C, the presented device is furthermore suitable for plastic substrates. Although hysteresis is observed, the inverter shows reasonable transfer characteristics with a gain of up to 5.5 V/V at a supply voltage between 10 V and 15 V, whereas the static power dissipation is lower than 6 μW.     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

Low Voltage and Ferroelectric 2D Electron Devices Using Lead‐Free BaxSr1‐xTiO3 and MoS2 Channel

Coupling between non‐toxic lead‐free high‐k materials and 2D semiconductors is achieved to develop low voltage field effect transistors (FETs) and ferroelectric non‐volatile memory transistors as well. In fact, low voltage switching ferroelectric memory devices are extremely rare in 2D electronics. Now, both low voltage operation and ferroelectric memory function have been successfully demonstrated in 2D‐like thin MoS₂ channel FET with lead‐free high‐k dielectric Ba_xSr_1‐xTiO₃ (BST) oxides. When the BST surface is coated with a 5.5‐nm‐ultrathin poly(methyl methacrylate) (PMMA)‐brush for improved roughness, the MoS₂ FET with BST (x = 0.5) dielectric results in an extremely low voltage operation at 0.5 V. Moreover, the BST with an increased Ba composition (x = 0.8) induces quite good ferroelectric memory properties despite the existence of the ultrathin PMMA layer, well switching the MoS₂ FET channel states in a non‐volatile manner with a ±3 V low voltage pulse. Since the employed high‐k dielectric and ferroelectric oxides are lead‐free in particular, the approaches for applying high‐k BST gate oxide for 2D MoS₂ FET are not only novel but also practical towards future low voltage nanoelectronics and green technology.     

Large‐Area Chemical Vapor Deposited MoS2 with Transparent Conducting Oxide Contacts toward Fully Transparent 2D Electronics

2D semiconductors are poised to revolutionize the future of electronics and photonics, much like transparent oxide conductors and semiconductors have revolutionized the display industry. Herein, these two types of materials are combined to realize fully transparent 2D electronic devices and circuits. Specifically, a large‐area chemical vapor deposition process is developed to grow monolayer MoS₂ continuous films, which are, for the first time, combined with transparent conducting oxide (TCO) contacts. Transparent conducting aluminum doped zinc oxide contacts are deposited by atomic layer deposition, with composition tuning to achieve optimal conductivity and band‐offsets with MoS₂. The optimized process gives fully transparent TCO/MoS₂ 2D electronics with average visible‐range transmittance of 85%. The transistors show high mobility (4.2 cm² V^?1 s^?1), fast switching speed (0.114 V dec^?1), very low threshold voltage (0.69 V), and large switching ratio (4 × 10⁸). To our knowledge, these are the lowest threshold voltage and subthreshold swing values reported for monolayer chemical vapor deposition MoS₂ transistors. The transparent inverters show fast switching properties with a gain of 155 at a supply voltage of 10 V. The results demonstrate that transparent conducting oxides can be used as contact materials for 2D semiconductors, which opens new possibilities in 2D electronic and photonic applications.     

Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process

Large array devices (LAD) of MOSFETs are needed in most power ICs. NMOS transistors are used in current sinking while PMOS in current driving. Unlike the NMOS transistors, the high voltage PMOS transistors (HVPMOS) electrostatic discharge (ESD) self-protection of LAD for higher than 30 V applications are less extensively studied. In this paper, the device level improvements of the 60 V HVPMOS LAD of a 0.25 μm BCD process is studied to obtain good ESD protection margins. The effects of device and layout optimization guidelines are also examined. Furthermore, the developed approach is shown to be a low cost general solution for the HVPMOS LAD with poor ESD self-protection capability in a 0.25 μm BCD process.     

Low-cost and flexible printed graphene–PEDOT:PSS gas sensor for ammonia detection

This work presents a simple, low-cost and practical inkjet-printing technique for fabricating an innovative flexible gas sensor made of graphene–poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) composite film with high uniformity over a large area. An electronic ink prepared by graphene dispersion in PEDOT:PSS conducting polymer solution is inkjet-printed on a transparency substrate with prefabricated electrodes and investigated for ammonia (NH₃) detection at room temperature. Transmission electron microscopy, Fourier transform infrared spectroscopy, UV–visible spectrometer and Raman characterizations confirm the presence of few-layer graphene in PEDOT:PSS polymer matrix and the present of π–π interactions between graphene and PEDOT:PSS. The ink-jet printed graphene–PEDOT:PSS gas sensor exhibits high response and high selectivity to NH₃ in a low concentration range of 25–1000 ppm at room temperature. The attained gas-sensing performance may be attributed to the increased specific surface area by graphene and enhanced interactions between the sensing film and NH₃ molecules via π electrons network. The NH₃-sensing mechanisms of the flexible printed gas sensor based on chemisorbed oxygen interactions, direct charge transfers and swelling process are highlighted.     

Enhanced performance of multilayer MoS2 transistor employing a polymer capping layer

Two-dimensional (2D) MoS₂ field-effect transistors (FETs) have attracted many attentions due to their intriguing electronic, optical, and mechanical properties. In this work, the electrical properties of multilayer MoS₂ FETs are significantly enhanced by using water-soluble polyvinyl alcohol (PVA) polymer as the capping layer. The key parameter, field-effect mobilities (μ), can be increased from 0.28 cm²/Vs to 269.2 cm²/Vs after applying the PVA capping layer, which means it has almost three orders of magnitudes increase. An energy band diagram based on Schottky barrier modulation is proposed to understand the device mechanism. The results represent a significant step towards applications of 2D MoS₂ FETs for future integrated circuit, sensors, and flexible electronics.     

High‐Gain Double‐Bulk Mixer in 65 nm CMOS with 830 pW Power Consumption

A low‐power down‐sampling mixer in a low‐power digital 65 nm CMOS technology is presented. The mixer consumes only 830 µW at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 °1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of ?5.9 dBm is achieved.     

Ultra-low-power temperature compensated voltage reference generator

A CMOS voltage reference generator, based on the difference between the gate-source voltages of two NMOS transistors, has been implemented with AMS 0.35 μm CMOS technology (V_thn=0.45 and at 0 °C). The minimum and maximum supply voltages that ensure the correct operation of the reference voltage generator, are 1.5 and 4.3 V, respectively. The supply current at the maximum supply voltage and at 80 °C is 2.4 μA. A temperature coefficient of 25 ppm/°C and a line sensitivity of 1.6 mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100 Hz and 10 MHz are larger than −74 and −59 dB, respectively. The occupied chip area is 0.08 mm².     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Organic inverter: Theoretical analysis using load matching technique

This paper reports the analysis of key parameters affecting voltage transfer characteristics of pseudo PMOS organic inverters. Pentacene has been used as active material for PMOS Organic Thin Film transistor (OTFT). We have used two different inverter configurations for thorough analysis. Each configuration comprises of an enhancement mode driver (V_Threshold = −9.7 V) and a depletion mode load (V_Threshold = 11.7 V). First configuration has its source and gate terminals shorted. While, second configuration differs with its drain and gate terminals shorted. In order to surmise the theoretical performance of the inverters, we have used load matching technique. After investigating various parameters such as inverting gain, noise margin values (immunity to noise error signals) and threshold voltage value, influencing the voltage inverting efficiency of the two configurations mentioned above, it was found that an inverter with shorted source-gate load configuration is better of the two due to privileges such as saturation mode operation of load, low driver current with early saturation of enhancement mode driver, which facilitates full swing output voltage operation. Second configuration with shorted drain-gate load, lacks saturation mode operation of load and fails to deliver high voltage swing along with acceptable noise margin values and inverting gain.     

Air-stability and bending properties of flexible organic field-effect transistors based on poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)]

We have fabricated flexible field-effect transistors (FETs) using poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)], PCDTBT, as an active channel, poly(methyl methacrylate) (PMMA) as gate dielectric and biaxially oriented polyethyleneterephthalate (BOPET) as supporting substrate. The output and transfer characteristics of the devices were measured as a function of channel length. It has been observed that various OFET parameters viz. on–off ratio (∼10⁵), mobility (μ ∼ 10⁻⁴ cm² V⁻¹ s⁻¹), threshold voltage (V_th ∼ −14 V), switch-on voltage (V_so ∼ −6 V), subthreshold slope (S ∼ 7 V/decade) and trap density (N_it ∼ 10¹⁴ cm⁻² V⁻¹) are almost independent of the channel length, which suggested a very high uniformity of the PCDTBT active layer. These devices were highly stable under atmospheric conditions (temperature: 20–35 °C and relative humidity: 70–85%), as no change in mobility was observed on a continuous exposure for 70 days. The studies on the effect of strain on mobility revealed that devices are stable up to a compressive or tensile strain of 1.2%. These results indicate that PCDTBT is a very promising active layer for the air stable and flexible FETs.