并五苯钝化层增强C60有机场效应晶体管性能的研究

We investigated the properties of C₆₀-based organic field-enect transistors（OFETs）（?） a pentacene passivation layer inserted between the C₆₀ active layer and the gate dielectric.After modification of the pentacene passivation layer,the performance of the devices was considerably improved compared to C₆₀-based OFETs with only a PMMA dielectric.The peak field-effect mobility was up to 1.01 cm²/（V·s） and the on/off ratio shifted to 10⁴.This result indicates that using a pentacene passivation layer is an effective way to improve the performance of N-type OFETs.     

Monitoring the Channel Formation in Organic Field‐Effect Transistors via Photoinduced Charge Transfer

Conducting channel formation in organic field‐effect transistors (OFETs) is considered to happen in the organic semiconductor layer very close to the interface with the gate dielectric. In the gradual channel approximation, the local density of accumulated charge carriers varies as a result of applied gate bias, with the majority of the charge carriers being localized in the first few semiconductor monolayers close to the dielectric interface. In this report, a new concept is employed which enables the accumulation of charge carriers in the channel by photoinduced charge transfer. An OFET employing C₆₀ as a semiconductor and divinyltetramethyldisiloxane‐bis(benzocyclobutene) as the gate dielectric is modified by a very thin noncontinuous layer of zinc‐phthalocyanine (ZnPc) at the semiconductor/dielectric interface. With this device geometry, it is possible to excite the phthalocyanine selectively and photogenerate charges directly at the semiconductor/dielectric interface via photoinduced electron transfer from ZnPc onto C₆₀. Thus the formation of a gate induced and a photoinduced channel in the same device can be correlated.     

Decoupling the Bias‐Stress‐Induced Charge Trapping in Semiconductors and Gate‐Dielectrics of Organic Transistors Using a Double Stretched‐Exponential Formula

A novel strategy for analyzing bias‐stress effects in organic field‐effect transistors (OFETs) based on a four‐parameter double stretched‐exponential formula is reported. The formula is obtained by modifying a traditional single stretched‐exponential expression comprising two parameters (a characteristic time and a stretched‐exponential factor) that describe the bias‐stress effects. The expression yields two characteristic times and two stretched‐exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer‐side of the interface and the gate‐dielectric layer‐side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate‐dielectric layer were varied systematically. It was found that the gate‐dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias‐stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self‐assembled monolayer further widens the distribution of the activation energy for charge trapping in gate‐dielectric layer‐side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.     

Improving Electrical Stability and Ideality in Organic Field‐Effect Transistors by the Addition of Fullerenes: Understanding the Working Mechanism

Electrical instability and nonideality due to undesirable electron injection are often‐encountered problems for high‐mobility organic field‐effect transistors (OFETs) with low‐bandgap polymer semiconductors. Due to electron trapping and the resulting accumulation of negative charges on the silicon dioxide dielectric, transfer curves deviate from ideality characteristics and double‐slopes are observed as the devices are operated for extended periods of time. One way to circumvent those is to use an electron‐acceptor additive, such as fullerene and its derivatives. This work interprets the mechanisms of how fullerene derivatives suppress electron transport and electrical instability while maintaining high hole mobility in p‐type OFETs. This study shows that hole transport of the active layer is uninterrupted upon the addition of the electron acceptors. Most importantly, the added fullerene derivatives out‐compete SiO₂ to acquire electrons that are injected into the polymers. Electrical instability and double‐slope induced from electron trapping at SiO₂ surface are thereby suppressed.     

Bias‐Stress‐Induced Charge Trapping at Polymer Chain Ends of Polymer Gate‐Dielectrics in Organic Transistors

Herein is demonstrated that the polymer chain ends of polymer gate‐ dielectrics (PGDs) in organic field‐effect transistors (OFETs) can trap charges; the bias‐stress stability is reduced without changes in the mobilities of the transistor devices as well as the morphologies of the organic semiconductors. The bias‐stress stabilities of OFETs using PGD with various molecular weights (MWs) are investigated. Under bias stress in ambient air, the drain current decay and the threshold voltage shift are found to increase as the MW of the PGD decreases (MW effect). This MW effect is caused by the variation in the density of polymer chain ends in the PGDs with MW: the free volumes at the polymer chain ends act as charge‐trap sites, resulting in drain current decay during bias stress. The free volumes at polymer chain ends are sufficiently large to allow the residence of water molecules, the presence of which significantly increases the density of charge‐trap sites. In contrast, polymer chain ends without trapped water molecules do not allow charge trapping and so bias‐stress stability is independent of the MW of the PGD. It is also found that the hydrophilicity/hydrophobicity of the chain ends of the PGD can affect bias‐stress stability; carboxyl‐terminated polystyrene exhibits a much higher trap density and lower bias‐stress stability than hydrogen‐terminated polystyrene when these devices are exposed to humid nitrogen.     

Polarity Effects of Polymer Gate Electrets on Non‐Volatile Organic Field‐Effect Transistor Memory

Organic non‐volatile memory (ONVM) based on pentacene field‐effect transistors (FETs) has been fabricated using various chargeable thin polymer gate dielectrics—termed electrets—onto silicon oxide insulating layers. The overall transfer curve of organic FETs is significantly shifted in both positive and negative directions and the shifts in threshold voltage (V_Th) can be systemically and reversibly controlled via relatively brief application of the appropriate external gate bias. The shifted transfer curve is stable for a relatively long time—more than 10⁵ s. However, this significant reversible shift in V_Th is evident only in OFETs with non‐polar and hydrophobic polymer electret layers. Moreover, the magnitude of the memory window in this device is inversely proportional to the hydrophilicity (determined from the water contact angle) and dielectric polarity (determined from the dielectric constant), respectively. Memory behaviors of ONVM originate from charge storage in polymer gate electret layers. Therefore, the small shifts in V_Th in ONVM with hydrophilic and polar polymers may be due to very rapid dissipation of transferred charges through the conductive channels which form from dipoles, residual moisture, or ions in the polymer electret layers. It is verified that the surface or bulk conductivities of polymer gate electret layers played a critical role in determining the non‐volatile memory properties.     

High performance n-channel thin-film field-effect transistors based on angular-shaped naphthalene tetracarboxylic diimides

We report on the performance of organic field-effect transistors (OFETs) by using a series of angular-shaped naphthalene tetracarboxylic diimides as active layers. The fabricated OFET devices exhibit n-type semiconducting characteristics. The performance of OFETs can be substantially improved by modifying the surface of the gate dielectric chemically prior to the deposition of the organic semiconductors. An increased electron mobility of the OFETs was found owing to the improved crystallinity and enlarged grain sizes, which are attributed to the elevating substrate temperature during the semiconductor deposition. The highest mobility of 0.515 cm²/V s was achieved from a device fabricated at substrate temperature of 130 °C with octadecyltrichlorosilane (OTS) surface modification.     

Modification of PCBM Crystallization via Incorporation of C60 in Polymer/Fullerene Solar Cells

The morphological effects of the incorporation of C₆₀ into blended thin‐films of poly(3‐hexylthiophene) and [6,6]‐phenyl C₆₁ butyric acid methyl ester (PCBM) are investigated. The results show that addition of C₆₀ readily alters the growth‐rate and morphology of PCBM crystallites under different environmental conditions. The effect of C₆₀ on the growth of large PCBM crystallites is thoroughly characterized using optical microscopy, electron microscopy and UV‐visible absorption spectroscopy. Results show that C₆₀ incorporation modifies fullerene aggregation and crystallization and greatly reduces the average crystallite size at C₆₀ loadings of ≈50 wt% in the fullerene phase. Organic field‐effect transistors (OFETs) are prepared to evaluate the electron mobility of PCBM/C₆₀ films and organic solar cells (OSCs) are fabricated from mixed‐fullerene active layers to evaluate their performance. It is demonstrated that the use of fullerene mixtures in organic electronic applications is a viable approach to produce more stable devices and to control the growth of micrometer‐sized fullerene crystals.     

Low-voltage p-channel, n-channel and ambipolar organic thin-film transistors based on an ultrathin inorganic/polymer hybrid gate dielectric layer

A key issue in research into organic thin-film transistors (OTFTs) is low-voltage operation. In this study, we fabricated low-voltage operating (below 3V) p-channel, n-channel and ambipolar OTFTs based on pentacene or/and C₆₀ as the active layers, respectively, with an ultrathin AlO_X/poly(methyl methacrylate co glycidyl methacrylate) (P(MMA–GMA)) hybrid layer as the gate dielectric. Benefited from the enhanced crystallinity of C₆₀ layer and greatly reduced density of electron trapping states at the interface of channel/dielectric due to the insertion of ultrathin pentacene layer between C₆₀ and P(MMA–GMA), high electron mobility can be achieved in present pentacene/C₆₀ heterostructure based ambipolar OTFTs. The effect of the thickness of pentacene layer and the deposition sequence of pentacene and C₆₀ on the device performance of OTFTs was studied. The highest electron mobility of 3.50 cm²/V s and hole mobility of 0.25 cm²/V s were achieved in the ambipolar OTFT with a pentacene (3.0 nm)/C₆₀ (30 nm) heterostructure.     

Air stable C60 based n-type organic field effect transistor using a perfluoropolymer insulator

Air stable n-type organic field effect transistors (OFETs) based on C₆₀ are realized using a perfluoropolymer as the gate dielectric layer. The devices showed the field-effect mobility of 0.049 cm²/V s in ambient air. Replacing the gate dielectric material by SiO₂ resulted in no transistor action in ambient air. Perfluorinated gate dielectric layer reduces interface traps significantly for the n-type semiconductor even in air.     

Reliability of thin ZrO2 gate dielectric layers

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO₂ gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (V_t) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.     

Employing microspectroscopy to track charge trapping in operating pentacene OFETs

Ultrathin pentacene films resemble benchmark and model materials for organic field-effect transistors (OFETs). We employ scanning transmission X-ray microspectroscopy (STXM) and confocal Raman microspectroscopy as highly resolving probes to obtain insight into the correlation of morphology and charge transport in pentacene OFETs. By combining the operation-induced intensity increase in Raman-active bands with micromorphology, we are able to visualize charge-induced effects, in particular charge trapping in pentacene OFETs during operation. The high sensitivity and specificity of Raman microscopy allows to distinguish between orientation and charge-induced effects and thus to locate the trapped charges at grain boundaries.     

The trapping,detrapping, and transport of the ambipolar charges in the electret of Polystyrene/C60 blend films

The electrons and holes were injected into the blend electrets of polystyrene and C₆₀ (PS/C₆₀) by adjusting the biases of conductive atomic force microscopy probe. We visualized the charges trapping, release, diffusion, and retention processes of the PS/C₆₀ electrets by utilizing the Kelvin Probe Force Microscopy (KPFM), and found that the localization and retention abilities of the ambipolar charges are enhanced with the increase of C₆₀ content, indicating that blending C₆₀ in PS matrix is a promising method for the charge trapping layer in transistor memory devices. Furthermore, we discussed the storage and diffusion mechanisms, and speculated that the interface of C₆₀ and PS in the blend electrets and repulsive force between charge clusters around C₆₀ are the important factors for the novel storage effect of the blend electret.     

Effects of film microstructure on the bias stability of pentacene field-effect transistors

In this report, the effects of film microstructure on the bias stability of pentacene field-effect transistors (FETs) were investigated. To control the microstructure of pentacene film, substrate temperature was changed from 25 to 90 °C during pentacene deposition. As the substrate temperature increased, pentacene grain size increased (or grain boundary (GB) decreased) because of the elevated surface diffusion of pentacene molecules. Accordingly, field-effect mobility increased up to 1.52 cm²/V. In contrast, bias stability showed totally different characteristics: samples prepared at high substrate temperatures exhibited the lowest degree of bias stability. This GB independent charge trapping phenomenon was solved by examining molecular scale ordering within the intragrain regions. The pentacene film grown at 90 °C showed the largest percentage of pentacene molecules with bulk crystalline structures. This inhomogeneity in the pentacene microstructure induces crystal mismatch within intragrain region, thereby providing deep trap sites for gate-bias stress driven instability. Our study shows that GB is not the main sites for bias stress related charge trapping, rather the molecular orientation within intragrain region is responsible for the charge trapping events. In this regard, the control of molecular scale ordering is important to obtain OFETs with a high bias stability.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Overcoming the “retention vs. voltage” trade-off in nonvolatile organic memory: Ag nanoparticles covered with dipolar self-assembled monolayers as robust charge storage nodes

Organic non-volatile memory devices with significantly enhanced retention are explored with C₆₀ thin-film transistors containing silver nanoparticles (Ag-NPs) within gate dielectrics as charge storage nodes. Dipolar self-assembled monolayers covering Ag-NPs effectively prevent stored charges from being lost by providing an additional energy threshold for back-tunneling process. This enables long retention even with ultrathin tunneling dielectric layers, providing a simple means to realize long retention without causing an excessive increase in operation voltage.     

Control of Ambipolar and Unipolar Transport in Organic Transistors by Selective Inkjet‐Printed Chemical Doping for High Performance Complementary Circuits

The selective tuning of the operational mode from ambipolar to unipolar transport in organic field‐effect transistors (OFETs) by printing molecular dopants is reported. The field‐effect mobility (μ_FET) and onset voltage (V_on) of both for electrons and holes in initially ambipolar methanofullerene [6,6]‐phenyl‐C61‐butyric acid methyl ester (PCBM) OFETs are precisely modulated by incorporating a small amount of cesium fluoride (CsF) n‐type dopant or tetrafluoro‐tetracyanoquinodimethane (F4‐TCNQ) p‐type dopant for n‐channel or p‐channel OFETs either by blending or inkjet printing of the dopant on the pre‐deposited semiconductor. Excess carriers introduced by the chemical doping compensate traps by shifting the Fermi level (E_F) toward respective transport energy levels and therefore increase the number of mobile charges electrostatically accumulated in channel at the same gate bias voltage. In particular, n‐doped OFETs with CsF show gate‐voltage independent Ohmic injection. Interestingly, n‐ or p‐doped OFETs show a lower sensitivity to gate‐bias stress and an improved ambient stability with respect to pristine devices. Finally, complementary inverters composed of n‐ and p‐type PCBM OFETs are demonstrated by selective doping of the pre‐deposited semiconductor via inkjet printing of the dopants.     

Role of geometry, substrate and atmosphere on performance of OFETs based on TTF derivatives

We report a comparative study of OFET devices based on zone-cast layers of three tetrathiafulvalene (TTF) derivatives in three configurations of electrodes in order to determine the best performing geometry. The first testing experiments were performed using SiO₂/Si substrates. Then the optimum geometry was employed for the preparation of flexible OFETs using Parylene C as both substrate and dielectric layer yielding, in the best case, to devices with μ_FET = 0.1 cm²/V s. With the performed bending tests we determined the limit of curvature radius for which the performance of the OFETs is not deteriorated irreversibly. The investigated OFETs are sensitive to ambient atmosphere, showing reversible increase of the source to drain current upon exposition to air, what can be explained as doping of TTF derivative by oxygen or moisture.     

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage (V _ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.