Improved pentacene growth continuity for enhancing the performance of pentacene-based organic thin-film transistors

This study proposes an alternative planar bottom-contact (pBC) structure to enhance the electrical performance of pentacene-based organic thin-film transistors (OTFTs). This pBC structure uses a bilayer dielectric to control planarization with a precise etch depth and introduces a bilayer photoresist lift-off method to ensure that planarization produces an optimum flatness. Because of the improved growth continuity of pentacene near the edge of the source/drain electrodes, the contact resistance between the source/drain and the pentacene was reduced significantly, thereby enhancing the electrical performance of OTFTs. The mechanism for the enhanced performance was also verified by a physics-based numerical simulation.     

Organic field-effect transistors based on single-crystalline active layer and top-gate insulator consistently fabricated by electrostatic spray deposition

An electrostatic spray deposition (ESD) method was applied to prepare both crystalline domains of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) and insulating films of poly(methyl methacrylate) (PMMA) for fabricating top-gate single-crystal organic field-effect transistors (OFETs). The electrical characteristics of the top-gate device were compared to those of the bottom-gate one (SiO₂ bottom-gate insulator) with the same active layer, and the lower charge-trap density at the interface between the top-gate insulator and single-crystalline active layer was demonstrated. The drain current compression in the output characteristics of the top-gate device, however, occurred due to the large parasitic resistance between the source/drain electrodes and accumulation channel. Reducing the thickness of the single-crystalline active layer resulted in a high charge-carrier mobility of 0.29 cm²/V s (channel length of 5 μm).     

Intrinsic difference in Schottky barrier effect for device configuration of organic thin-film transistors

Schottky barrier effect for n-channel organic thin-film transistors (OTFTs) with bottom-gate, top-contact (TC) and bottom-gate, bottom-contact (BC) configuration was examined by using device simulation with a thin-film organic transistor advanced simulator (TOTAS). A thermionic field emission (TFE) model which addresses tunneling of thermally excited electrons was applied as a carrier injection model of OTFTs. Simulation results reveal that the BC configuration is affected by Schottky barrier more severely than the TC configuration under the same condition for device parameters, and that this discrepancy in device characteristics can be completely alleviated by contact-area-limited doping, where highly-doped semiconducting layers are prepared in the neighborhood of contact electrodes. Moreover, the existence of an intrinsic Schottky barrier is indicated even though an ohmic-contact condition is assumed, which becomes more prominent for lower bulk carrier concentration in organic semiconductor. This work suggests the availability of the TFE model for simulating realistic OTFT devices with Schottky contacts. From the simulation results, intrinsic differences in device performance for the TC and BC configurations are discussed.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.     

Two-step surface modification for bottom-contact structured pentacene thin-film transistors

We investigated surface treatment effects of hexamethyldisilazane (HMDS), poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) and l-cysteine on gold source/drain electrodes in bottom-contact structured pentacene thin-film transistors (TFTs). The treatment methods include spin coating and immersing. We have also researched on two-step treatment based on the combination of each treatment methods. The highest device performance was achieved by treating gold S/D electrodes with l-cysteine first and PEDOT:PSS afterwards, showing field effect mobility up to 0.35 cm²/V·s. l-cysteine can reduce the contact resistance between metal and semiconductor layer, and PEDOT:PSS acted as a hole transporting layer while HMDS decreased the surface energy, which enlarged the grain size of pentacene on it.     

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φ_b = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10⁵ V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |V_ds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V_ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |V_ds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.     

Fabrication,characterization,numerical simulation and compact modeling of P3HT based organic thin film transistors

This paper presents the fabrication,characterization and numerical simulation of poly-3-hexylthiophene (P3HT)-based bottom-gate bottom-contact (BGBC) organic thin film transistors (OTFTs).The simulation is based on a drift diffusion charge transport model and density of defect states (DOS) for the traps in the band gap of the P3HT based channel.It com-bines two mobility models,a hopping mobility model and the Poole-Frenkel mobility model.It also describes the defect dens-ity of states (DOS) for both tail and deep states.The model takes into account all the operating regions of the OTFT and in-cludes sub-threshold and above threshold characteristics of OTFTs.The model has been verified by comparing the numerically simulated results with the experimental results.This model is also used to simulate different structure in four configurations of OTFT e.g.bottom-gate bottom-contact (BGBC),bottom-gate top-contact (BGTC),top-gate bottom-contact (TGBC) and top-gate top-contact (TGTC) configurations of the OTFTs.We also present the compact modeling and model parameter extraction of the P3HT-based OTFTs.The extracted compact model has been further applied in a p-channel OTFT-based inverter and three stage ring oscillator circuit simulation.     

Enhanced Charge Injection Through Nanostructured Electrodes for Organic Field Effect Transistors

Nanosphere lithography is used to process nanopore‐structured electrodes, which are applied into the fabrication of bottom‐gate, bottom‐contact configuration organic field effect transistors (OFETs) to serve as source/drain elecrodes. The introduction of this nanopore‐structure electrode facilitates the forming of nanopore‐structure pentacene layers with small grain boundaries at the electrode interface, and then reduces the contact resistance, contact‐induces the growth of pentacene and accordingly improves the mobility of charge carriers in the OFETs about 20 times as compared with results in literature through enhancing the charge carrier injection. It is believed that this structure of electrode is a valuable approach for improving organic filed effect transistors.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring I_DS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at V_{DS =} 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel.     

Bottom-contact poly(3,3‴-didodecylquaterthiophene) thin-film transistors with reduced contact resistance

A dramatic, ∼20-fold, reduction in the contact resistance of the bottom-contact poly(3,3‴-didodecylquaterthiophene) (PQT-12) thin-film transistors was achieved through a simple treatment of gold (Au) source and drain electrodes. The Au electrode treatment involved simply immersing the Au electrodes into Piranha solution prior to the deposition of the organic semiconductor. This treatment led to significant improvement of device performance. Channel length scaling analysis indicates that the contact resistance is reduced by about one order of magnitude, resulting in enhancement of estimated field-effect mobility by about a factor of five. Transport characteristic analysis suggests that the improved efficiency of charge carrier injection is probably due to increased dopant density of PQT-12 at the electrode/PQT-12 interface.     

Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate

Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.     

A unified simulation of Schottky and ohmic contacts

The Schottky contact is an important consideration in the development of semiconductor devices. This paper shows that a practical Schottky contact model is available for a unified device simulation of Schottky and ohmic contacts. The present model includes the thermionic emission at the metal/semiconductor interface and the spatially distributed tunneling calculated at each semiconductor around the interface. Simulation results of rectifying characteristics of Schottky barrier diodes (SBD's) and resistances under high impurity concentration conditions are reasonable, compared with measurements. As examples of application to actual devices, the influence of the contact resistance on salicided MOSFETs with source/drain extension and the immunity of Schottky barrier tunnel transistors (SBTTs) from the short-channel effect (SCE) are demonstrated     

Relation between injection barrier and contact resistance in top-contact organic thin-film transistors

We theoretically investigate the carrier injection into top-contact bottom-gate organic thin film transistors. By means of a two-dimensional drift–diffusion model, we explicitly consider thermionic and tunneling injection in combination with subsequent carrier transport into the device. Based on numerical simulations with this model, we determine the contact resistance as a function of the nominal hole injection barrier height and temperature. Depending on the barrier height or the operating temperature, we find three distinct injection regimes. Our work reveals that in all three regimes self-regulating processes exist due to which the influx of current is adjusted according to the needs of the channel at the given point of operation.     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. II. Quantitative analysis

Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime. The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction region, and the Schottky barrier height of the silicide contact. A prediction of series resistance trends with technology generation indicates that silicide-diffusion contact resistance and overlap resistance will be major components in the total series resistance of nanometer-scale CMOS transistors scaled according to the ITRS roadmap. The key factors for challenging scaling barriers related to parasitic resistance are quantitatively examined as a function of technology scaling and it is shown that the series resistance can be substantially reduced through controlling both the abruptness of the S/D junction profile and the silicide Schottky barrier engineering     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

石墨烯电极有机薄膜晶体管研究

利用化学气相沉积法生长的高性能的层状石墨烯,通过转移和图案化后用作电极,制备了底接触的并五苯有机薄膜晶体管(OTFTs)。原子力显微镜观察发现,石墨烯电极的厚度比一般的金电极薄的多,所以石墨烯电极厚度对并五苯晶粒的生长影响不大。电学性能研究得到器件的输出和转移曲线、开关电流比、阈值电压、场效应迁移率。转移曲线的关态电流约为10-9 A,电流的开关比超过103。基于底接触的并五苯OTFTs的最大场效应迁移率约2×10-2 cm2.V-1.s-1。     

Enhanced Gate Swing in InP HEMTs With High Threshold Voltage by Means of InAlAsSb Barrier

We demonstrated the suitability of the InP HEMTs with the InAlAsSb Schottky barrier to realize the high threshold voltage (enhancement mode), low gate current, and low power consumption. This quaternary compound material increases the conduction band discontinuity to the InGaAs channel by introducing only 10% of antimony to InAlAs. The gate current is reduced by an order of the magnitude (or even more) at gate voltage range from 0.4 to 0.8 V. On the other hand, the large conduction band discontinuity causes larger parasitic source and drain resistance, which decreases the extrinsic transconductance. Nevertheless, the high-frequency performance is comparable to the device with the conventional InAlAs barrier layer. Therefore, the InAlAsSb barrier is a promising option for logic applications, which requires reduced gate current. FETs, gate current, high-electron mobility transistors (HEMTs), high frequency.     

Contact-resistance effects in PDI8-CN2 n-type thin-film transistors investigated by Kelvin-probe potentiometry

In this paper, the metal-semiconductor contacts in n-type bottom-contact bottom-gate Organic Field-Effect Transistors (OFET), based on evaporated films of a perylene diimide derivative (PDI8-CN₂), have been investigated by Scanning Kelvin Probe Microscopy (SKPM). OFET were characterized for different thicknesses of the PDI8-CN₂ film and in the light of the gold electrode functionalization with an aromatic thiol self-assembled monolayer. SKPM experiments reveal that aromatic thiol functionalization produces a 30% reduction in the contact resistance (R_c), while lowering the organic film thickness, the contact resistance (R_c) phenomenon tends to be magnified. The experimental observation that the voltage drops occurring close the drain electrode are even larger than those taking place at the source contact suggests that it is not possible, for these devices, to explain the overall R_c effects by simply referring to the presence of a reverse-biased Schottky junction limiting the electron injection process into the active channel.     

High performance submicrometer pentacene-based organic thin-film transistor using planar bottom-contact structure

This paper presents a pentacene-based organic thin-film transistor (OTFT) with a submicrometer channel length of 0.5 μm that uses a planar bottom-contact (pBC) structure to achieve high electrical performance. The performance of the submicrometer OTFT is dominantly influenced by the growth continuity of pentacene near the edge of the source/drain (S/D). The pBC structure with a bilayer dielectric can provide a continuous plane for improving the growth continuity and quality of pentacene near the edge of the S/D. This results in high electrical performance for the submicrometer OTFT with pBC structure, such as a mobility of 0.14 cm²/V s and an on/off current ratio of 1.9 × 10⁵.