CMOS active pixel image sensors fabricated using a 1.8-V,0.25-μm CMOS technology

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-μm CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.     

Design and analysis of a 512×768 current-mediated activepixel array image sensor

Current-mediated, current-output active pixels offer the advantages of compact size and simple operation in designing large format CMOS image sensors, with performance limited by spatial fixed pattern noise. In this paper, a thorough noise analysis is made of the expected performance of a current-output pixel image sensor. This analysis is compared with experimental results from a 512×768 array imager fabricated in a 0.7 μm process, and the effectiveness of basic error correction techniques are explored. The goal of this study was to determine the performance limits of this device and to gain insight into the design issues needed to develop a high-quality current-output imager     

CMOS scaling for high performance and low power-the next ten years

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 μm channel length at 2.5 V down to sub-0.1 μm at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7× and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 μm regime as compared with today's high performance 0.6 μm devices at 5 V. However, the power density rises by a factor of 4× for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3× savings in power compared to the bulk case at the same speed     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively     

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0×10⁵ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 μm(H)×5.2 μm(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager     

A small pixel CMD image sensor

A charge modulation device (CMD) imager with pixel dimensions of 7.3 μm(H)×7.6 μm(V) was designed, fabricated, and examined. These pixel dimensions are suitable for an HDTV imager with a 1-in image format. The optical aperture ratio is 34%. The effective number of pixels in the imager is 660 horizontal and 492 vertical. The saturation signal current is 17 μA/pixel at an exposure of 1 lx-s with good linearity of photoconversion characteristics. The peak of its spectral response occurs at a wavelength of 575 nm. The blooming suppression ratio of the CMD was measured to be -122 dB. The sensor produces a high-quality image with no degradation in spatial resolution and no image lag. These features show that the CMD imager is eminently suitable for a further high-resolution imager sensor     

Integration challenges in sub-0.25 μm CMOS-based technologies

Market demands, which require increased functionality at lower costs are driving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations.Current research and development activities in CMOS technology are focused on scaling CMOS technologies below 0.25 μm dimensions. While some of the process modules can be scaled down in a conventional way, in some cases severe limitations are reached and it is necessary to introduce major modifications to the process flow.In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 or 0.13 μm CMOS technology generation.     

Sensitivity of CMOS based imagers and scaling perspectives

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors are reviewed with regard to their potential to allow meaningful comparison of different detector structures. In the main section, the standard CMOS sensor architecture is compared to detector structures designed to improve the sensitivity, namely the photogate (PG), the pinned photodiode (PPD) and the thin film on ASIC (TFA) approach. The latter uses a vertical integration of the photodiode on top of the pixel transistors. A careful analysis of the relevant electrical, optical and technological parameters and many previously published experimental data for different imagers reveals that only the PPD and the TFA enhancements provide satisfactory sensitivity and withstand scaling down to 0.18 μ processes. Due to the higher fill factor and the higher quantum efficiency TFA provides significantly better values than PPD. The radiometric sensitivity of a 5 μm×5 μm TFA pixel is found to amount to 11.9 V/(μ/cm²) for a 0.25 μm process and 27.5 V/(μJ/cm²) for a 0.18 μm process     

A high gain n-well/gate tied PMOSFET image sensor fabricated from astandard CMOS process

The performance of a high gain photodetector fabricated using a standard 0.8-μm, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular to the current flow. The n-well potential modulated by illumination is fed back to the gate through the well-to-gate connection, which results in an extra current amplification beyond that of a normal PMOSFET biased in the lateral bipolar mode. A high responsivity of 2.5×10³ A/W has been measured with an operating voltage as low as 0.3 V for a W/L of 8.2 μm/0.8 μm. The impact of technology scaling on the performance of the photodetector are also studied. A simple 32×32-pixel image sensor array was fabricated to demonstrate the feasibility of integrating the new device in actual circuit applications     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions     

A high-dynamic-range CMOS image sensor for automotive applications

In this paper, a 256×256 pixel CMOS imager is described that exhibits 120 dB dynamic range, 56 dB signal-to-noise ratio (SNR), 65% fill factor, and an effective frame rate of 50 Hz. This has been achieved using a unique combination of a multiexposure and a multigain linear readout. The imager has been integrated in 1 μm double-metal CMOS technology. The intended application is for driver's assistant systems, but the imager can be used for a wide range of applications requiring high dynamic range     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

Arbitrated address-event representation digital image sensor

An 80×60 pixels arbitrated address-event imager has been designed and fabricated in a 0.6 μm CMOS process. The output bandwidth is allocated according to the pixel's demand. The imager has a large dynamic range: 200 dB (pixel) and 120 dB (array). The power consumption is 3.4 mW in uniform indoor light. The imager is capable of 8.3 K effective frames per second     

Silicon bipolar device structures for digital applications:technology trends and future directions

The double-polysilicon self-aligned bipolar device structure has come a long way since its first inception, but there is still room for further scaling of this structure and continued improvements in performance. An analysis of the current state-of-the-art double-poly structure leads naturally to a discussion of future trends and technologies necessary to continue scaling into the sub-0.25 μm regime. In addition, it has become highly desirable to extend bipolar processes in new directions to take advantage of the opportunities offered by emerging materials technologies, such as bonded silicon-on-insulator films and medium or low temperature Si and SiGe epitaxy. Opportunities also exist for high-performance bipolars in BiCMOS technology and in complementary bipolar processes for low-power, high-speed digital applications. These extensions beyond “conventional” bipolar technology will be discussed in terms of their requirements and the device structures that are evolving to match these needs     

1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits     

Electrical limitations of advanced LOCOS isolation for deepsubmicrometer CMOS

Limitations to advanced local oxidation of silicon (LOCOS) based dielectric isolation of the poly buffer type are examined by fabricating CMOS devices with active area widths and spaces to 200 nm. Measured results show that device width scaling to 400 nm is possible using the retrograde-well process. The impact of narrow-channel effects, field oxide thinning, and drain-induced barrier lowering (DIBL) of the field oxide transistors on deep submicrometer CMOS has been quantified. For a retrograde-well process the narrow-channel effect is minimal for active device widths to 0.4 μm. DIBL is shown to limit the active device spacing to about 0.8 μm. SUPREM-4 and PISCES-2B simulations are utilized to illustrate the mechanism for the loss of isolation     

Technology challenges for integration near and below 0.1 μm

Technology challenges for silicon integrated circuits with a design rule of 0.1 μm and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 μm currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 μm which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 μm technology. 0.1 μm technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 μm are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 μm are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 μm is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput     

An enhanced-performance CMOS imager with a flushed-reset photodiode pixel

A new front-end for photodiode-based CMOS imagers is presented. Degradation in imaging performance due to conventional hard- and soft-reset of pixels is analyzed. To overcome these limitations, the design and operation of a flushed-reset pixel is described. The flushed-reset pixel combines the best of hard- and soft-reset to simultaneously provide excellent radiometric accuracy, high linearity, no image lag, high saturation level, and reduced read-noise. The new front-end is implemented by changes to the column-circuitry only, leaving the pixel unchanged, preventing degradation of any unrelated imaging performance. It is compatible with large format imager implementation, has minimal impact on the frame-rate, and does not introduce any additional hot-carrier stress in the pixel. Data from a large format (512/sup 2/) imager demonstrates the efficacy of the flushed-reset pixel approach.     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies