Incorporating Common-Cause Failures Into the Modular Hierarchical Systems Analysis

This paper considers the problem of evaluating the reliability of hierarchical systems subject to common-cause failures (CCF); and dynamic failure behavior such as spares, functional dependence, priority dependence, and dependence caused by multi-phased operations. We present a separable solution that has low computational complexity, and which is easy to integrate into existing analytical methods. The resulting approach is applicable to Markov analyses, and combinatorial models for the modular analysis of the system reliability. We illustrate the approach, and the advantages of the proposed approach, through the detailed analyses of two examples of dynamic hierarchical systems subject to CCF.      

A Unified Method for Analyzing Mission Reliability for Fault Tolerant Computer Systems

A reliability model is proposed and evaluated for a fault tolerant computer system which consists of multiple classes of modules and allows for degraded modes of performance. Each module of a given class has both an active and a passive hazard rate; constant hazard rates are assumed for active and dormant failures, and the given class may operate either in N Modular Redundancy (NMR: n + 1 out of 2n + 1 = N) or as a standby sparing system. The model allows for mission-phase changes at deterministic time points when the numbers of modules per class can be changed. The analysis proceeds by generalizing the notions of standby and NMR redundancy, which for N = 3 is TMR (Triple Modular Redundancy), into a concept called hybrid-degraded redundancy. The probabilistic evaluation of the unified redundancy concept is then developed to yield, for a given modular class, the joint distribution of success and the number of nonfailed modules from that class, at special times. With this information, a Markov chain analysis gives the reliability of an entire sequence of phases (mission profile).     

Reliability Analysis of Phased-Mission System With Independent Component Repairs

This paper proposes a hierarchical modeling approach for the reliability analysis of phased-mission systems with repairable components. The components at the lower level are described by continuous time Markov chains which allow complex component failure/repair behaviors to be modeled. At the upper level, there is a combinatorial model whose structure function is represented by a binary decision diagram (BDD). Two BDD ordering strategies, and consequently two evaluation algorithms, are proposed to compute the phased-mission system (PMS) reliability based on Markov models for components, and a BDD representation of system structure function. The performance of the two evaluation algorithms is compared. One algorithm generates a smaller BDD, while the other has shorter execution time. Several examples, and experiments are presented in the paper to illustrate the application, and the advantages of our approach.     

Distributed fault detection for modular and reconfigurable robots with joint torque sensing: A prediction error based approach

A distributed fault detection scheme for modular and reconfigurable robots (MRRs) with joint torque sensing is proposed in this paper. With the proposed scheme, the joint torque command is filtered and compared with a filtered torque estimate derived from the nonlinear dynamic model of MRR with joint torque sensing. Common joint actuator faults are considered with fault detection being performed independently for each joint module. The proposed fault detection scheme for each module does not require motion states of any other module making it an ideal modular approach for fault detection of modular robots. Experimental results have confirmed the effectiveness of the proposed fault detection scheme.     

基于动静态频谱相结合的接纳控制机制

在不同频段频谱共存的情况下,针对动静态频谱资源相结合的接入策略和接纳控制机制进行了研究.提出了一种支持动静态频谱资源相结合的非随机接入机制,利用排队论建立了相应的马尔可夫转移模型,定义了联合接纳控制因子,根据用户的需求不同设定了不同的控制因子门限值.启动接纳控制算法,以相应的概率来接纳新的呼叫请求.仿真结果表明,启动接纳控制算法后,用户的阻塞率、强制中断概率、联合接纳控制因子都得到了一定的改善.     

3C strategy for inverters in parallel operation achieving an equalcurrent distribution

A circular chain control (3C) strategy for inverters in parallel operation is presented in the paper. In the proposed inverter system, all the modules have the same circuit configuration, and each module includes an inner current loop and an outer voltage loop control. A proportional-integral controller is adopted as the inner current loop controller to expedite the dynamic response, while an H^∞ robust controller is adopted to reach the robustness of the multimodule inverter system and to reduce possible interactive effects among inverters. With the 3C strategy, the modules are in circular chain connection and each module has an inner current loop control to track the inductor current of its previous module, achieving an equal current distribution. Simulation results of two-module and a three-module inverter systems with different kinds of loads and with modular discrepancy have demonstrated the feasibility of the proposed control scheme. Hardware measurements are also presented to verify the theoretical discussion     

A modular control scheme for PMSM speed control with pulsating torque minimization

In this paper, a modular control approach is applied to a permanent-magnet synchronous motor (PMSM) speed control. Based on the functioning of the individual module, the modular approach enables the powerfully intelligent and robust control modules to easily replace any existing module which does not perform well, meanwhile retaining other existing modules which are still effective. Property analysis is first conducted for the existing function modules in a conventional PMSM control system: proportional-integral (PI) speed control module, reference current-generating module, and PI current control module. Next, it is shown that the conventional PMSM controller is not able to reject the torque pulsation which is the main hurdle when PMSM is used as a high-performance servo. By virtue of the internal model, to ify the torque pulsation it is imperative to incorporate an internal model in the feed-through path. This is achieved by replacing the reference current-generating module with an iterative learning control (ILC) module. The ILC module records the cyclic torque and reference current signals over one entire cycle, and then uses those signals to update the reference current for the next cycle. As a consequence, the torque pulsation can be reduced significantly. In order to estimate the torque ripples which may exceed certain bandwidth of a torque transducer, a novel torque estimation module using a gain-shaped sliding-mode observer is further developed to facilitate the implementation of torque learning control. The proposed control system is evaluated through real-time implementation and experimental results validate the effectiveness.     

基于动态故障树的惯导系统安全性分析

惯导系统是导弹的核心组成部分,其工作过程呈现一系列动态特性.为了获得惯导系统发生事故的可能性并查出可能导致事故的薄弱环节,在利用动态故障树方法对其进行安全性分析的基础上,建立了惯性平台倒台事故的动态故障树模型.然后将动态故障树模型模块化为独立的静态子树和动态子树,并分别利用二元决策图及Markov状态转移法进行了分析,...     

High-speed CMOS adder and multiplier modules for digital signalprocessing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology     

The Conro modules for reconfigurable robots

The goal of the Conro Project is to build deployable modular robots that can reconfigure into different shapes such as snakes or hexapods. Each Conro module is, itself, a robot and hence a Conro robot is actually a multirobot system. In this paper we present an overview of the Conro modules, the design approach, an overview of the mechanical and electrical systems and a discussion on size versus power requirement of the module. Each module is self-contained; it has its own processor, power supply, communication system, sensors and actuators. The modules, although self-contained, were designed to work in groups, as part of a large modular robot. We conclude the paper by describing some of the robots that we have built using the Conro modules and describing the miniature custom-made Conro camera as an example of the type of sensors that can be carried as payload by these robots.     

Effects of redundancy management on reliability modeling

Two methods are investigated for incorporating the effects of fault detection and isolation (FDI) decision errors and redundancy management (RM) policy into reliability models for a simple single-component-dual-redundant system. These two methods are combinatorial analysis and Markov chain modeling. Reliability analysts have traditionally chosen the classical combinatorial approach. However, the authors show that the existence of time-ordered event sequences resulting from the interaction of FDI decision errors with the RM policy considerably complicates the construction of the combinatorial model. An error analysis illustrates that a simplified combinatorial model, which ignores these time-ordered event sequences, inaccurately predicts the system reliability. The Markov modeling technique is an excellent alternative to the combinatorial approach because it easily and accurately accounts for time-ordered event sequences such as those present in fault-tolerant systems     

Real-time DSP implementation for MRF-based video motion detection

This paper describes the real time implementation of a simple and robust motion detection algorithm based on Markov random field (MRF) modeling, MRF-based algorithms often require a significant amount of computations. The intrinsic parallel property of MRF modeling has led most of implementations toward parallel machines and neural networks, but none of these approaches offers an efficient solution for real-world (i.e., industrial) applications. Here, an alternative implementation for the problem at hand is presented yielding a complete, efficient and autonomous real-time system for motion detection. This system is based on a hybrid architecture, associating pipeline modules with one asynchronous module to perform the whole process, from video acquisition to moving object masks visualization. A board prototype is presented and a processing rate of 15 images/s is achieved, showing the validity of the approach.     

Thermal reliability prediction and analysis for high-density electronic systems based on the Markov process

Thermal-mechanical fatigue is one of the main failure modes for electronic systems, particularly for high-density electronic systems with high-power components. Thermal reliability estimation and prediction have been an increasing concern for improving the safety and reliability of electronic systems. In this paper, we propose a stochastic process prediction model to estimate the thermal reliability of an electronic system based on Markov theory. We first divided the high-density electronic systems into four modules: the energy transformation and protection module, the electronic control module, the connection module, and the signal transmission and transformation module. By integrating failure and repair characteristics of the four modules, a stochastic model of thermal reliability analysis and prediction for a whole electronic system was built based on the Markov process. The feature parameters of thermal reliability evaluation, including thermal reliability, thermal failure probability, mean time between thermal faults, and thermal stable availability, were derived based on our comprehensive model. Finally, we applied the model to an indoor electronic system of DC frequency conversion conditioning. The thermal reliability was estimated and predicted using tested failure and debugging repair data. Effective methods for improving thermal reliability are presented and analyzed based on the comprehensive Markov model.     

Reliability analysis of recovery blocks with nested clusters offailure points

A Markov model is developed to obtain first and second moments of the number of successfully processed input-points for recovery blocks with a primary module and two alternate modules. A nested structure of clusters of failure points is assumed. When in a failure cluster of the primary module, the input sequence encounters clusters of failure points belonging to the first alternate module, in which case the second alternate is invoked. Some special cases are discussed in detail. A Markov chain model for one of the well-documented fault-tolerant software techniques, the recovery block, is analyzed. The model is intended to study recovery block reliability when the sequence of input values traverses nested clusters of failure points in the input domain. The method of solution exploited the specific structure of the state-transition diagram, which is two-dimensional. Moments of the number of successfully processed input points were obtained by recursively solving infinite systems of linear equations     

基于无线CPU的车载定位终端的设计与实现

介绍了车载定位终端的主要功能,叙述了系统工作原理和Open AT开发工具的组成,详细论述了车载定位终端的硬件设计和系统软件模块化设计,阐述了主程序、系统管理模块和各子模块的功能,给出了工作原理框图、硬件结构框图、系统管理模块初始化程序流程图及定时器中断处理函数流程图.     

基于Pspice的测试性验证与评估系统的设计

针对基于Pspice仿真开发的测试性验证与评估系统的使用测试性进行研究。该系统以PXI总线信号转接模块作为系统的硬件平台,采用硬件与软件相结合的方式进行,使用配置文件实现软、硬模块之间的信息交换和资源的动态调用。此方法可使测试性验证和评估摆脱对硬件系统和装备实体的依赖,使得装备在研制阶段、定型或验收阶段,不需要样本就可以进行测试性的验证与评估,为雷达装备测试性验证和评估提供了一条新的有效的途径。该系统经验证能够实现软、硬模块之间的信息交换和资源的动态调用。     

Enabling efficient reprogramming through reduction of executable modules in networked embedded systems

We present a systematic modular design approach for networked embedded systems. We effectively reduce the module file size to enable efficient network reprogramming, while at the same time retain necessary information to maintain module flexibility. We further handle module dependencies in a fine-grained manner, which improves system reliability while keeping the system configuration to its minimum requirement. We have implemented the modular approach based on a micro embedded OS, SenSpire OS, for AVR and MSP430 platforms. The evaluation results show that the proposed SELF module file format is 4.6–7.6 times smaller than the standard ELF format, and is 1.6–2.4 times smaller than the CELF format (a Compact ELF format for the Contiki OS). SELF retains necessary information to enable flexible modular programming and inter-module communications. We have further developed a long-term energy efficiency model to explore the tradeoffs of different reprogramming approaches.     

A separable method for incorporating imperfect fault-coverage intocombinatorial models

This paper presents a new method for incorporating imperfect FC (fault coverage) into a combinatorial model. Imperfect FC, the probability that a single malicious fault can thwart automatic recovery mechanisms, is important to accurate reliability assessment of fault-tolerant computer systems. Until recently, it was thought that the consideration of this probability necessitated a Markov model rather than the simpler (and usually faster) combinatorial model. SEA, the new approach, separates the modeling of FC failures into two terms that are multiplied to compute the system reliability. The first term, a simple product, represents the probability that no uncovered fault occurs. The second term comes from a combinatorial model which includes the covered faults that can lead to system failure. This second term can be computed from any common approach (e.g. fault tree, block diagram, digraph) which ignores the FC concept by slightly altering the component-failure probabilities. The result of this work is that reliability engineers can use their favorite software package (which ignores the FC concept) for computing reliability, and then adjust the input and output of that program slightly to produce a result which includes FC. This method applies to any system for which: the FC probabilities are constant and state-independent; the hazard rates are state-independent; and an FC failure leads to immediate system failure     

BDD-based reliability analysis of phased-mission systems with multimode failures

This paper proposes a new algorithm (DEP-BDD) based on binary decision diagram (BDD) for reliability analysis of phased-mission systems (PMS) with multimode failures. DEP-BDD is a BDD-based combinatorial model which can be used to deal with more than one kind of dependences by applying dependence algebra, which is a generalization of phase algebra that handles more complex dependences. The nature of the BDD contributes the efficiency and low computational complexity of this algorithm. Two examples are analysed to illustrate the applications and advantages of our approach.     

A synchronous approach for clocking VLSI systems

Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.