Silicon etched-groove permeable base transistors with 90-nm fingerwidth

Silicon etched-groove permeable base transistors (PBTs) which utilize a new structure to eliminate surface depletion effects are discussed. The 90-nm-wide fingers are n⁺-doped, and the channel region is buried below the bottom of the grooves. Doping and thickness of the active layer were optimized using two-dimensional computer simulations. The maximum measured transconductance of 155 mS/mm is the highest reported for Si PBTs and demonstrates the potential of silicon as substrate material. The measured transit frequency was 12 GHz; f_max reached 13 GHz. It has been recognized that for improved high-frequency performance a reduction of the gate capacitance is necessary, demanding a more precise control of groove depth and geometry     

Low-frequency noise in permeable base transistors

The predominant noise is1/fnoise and consists of two parts: a) Noise varying asImin{C}max{2}, generated mostly with conducting channel and predominating for normal values of the collector voltage VCE. b) Noise at low VCEand practically independent of VCE; it is generated chiefly in the space charge region around the base grating and gives collector1/fnoise atV_{CE} = 0. The turnover frequency of the first noise source lies at about 20 MHz forV_{CE} = 0.30V,V_{BE} = 0.20V. At sufficiently high frequencies the PBT shows thermal noise of the output conductanceg_{c0}at zero bias. Generation-recombination noise is observed at large VBEand low VCEand comes mostly from the space charge region around the base grating.     

Physics-based modeling of submicron GaN permeable base transistors

We present the first physics-based nonstationary modeling of a submicron GaN permeable base transistor. Three different transport models are compared: drift-diffusion, energy balance, and ensemble Monte Carlo. Transport parameters and relaxation times used by the carrier transport equations are consistently derived from particle simulation. The current-voltage (I-V) characteristics predicted with the energy balance model are in good agreement with those obtained from direct Monte Carlo device simulation. On the other hand, the drift-diffusion approach appears to be inadequate for the device under study, even if improved high-field mobility models are adopted     

Resonant tunneling permeable base transistors with high transconductance

A GaAs-based resonant tunneling permeable base transistor has been developed and evaluated at room temperature. The transistor is fabricated by overgrowing a tungsten gate placed next to an AlGaAs-GaAs-InGaAs resonant tunneling heterostructure. By changing the gate voltage, the effective conducting area of the tunnel diode can be modulated and the collector-emitter current thus controlled. Peak currents above 300 mA/mm and a maximum transconductance of 270 mS/mm have been obtained.     

Silicon epitaxial growth using dichlorosilane

This paper describes the results obtained growing silicon epitaxial structures in a horizontal reactor using dichlorosilane as the silicon source material. The growth rate dependence upon temperature and dichlorosilane flux has been obtained for rates ranging from 1 μm/min to 20 μm/min for all major crystal orientations. Characterization was carried out using spreading resistance measurements, IR interference, preferential etching, and optical microscopy, for layer thicknesses ranging from 3 μm to 250 μm. The majority of the structures grown were multi-layered, intended for use in fabricating high voltage power transistors. Controlled doping levels over the range 5 × 10¹³ to 1 × 10¹⁷ were obtained using either AsH³ or B²Hg⁶ as the dopant source. The effect of growth parameters on the doping profile and quality of such layers is described. Operating devices fabricated from this material exhibit bulk avalanche breakdown voltage. Large area npn transistors with collector base voltages greater than 2000 volts and current gains of 10 to 30 have also been fabricated.     

RTS noise in submicron SiGe epitaxial base bipolar transistors

In this paper, we report a comprehensive study of Random Telegraph Signal (RTS) noise in SiGe epitaxial base bipolar transistors. We analyse the multilevel fluctuations of base and emitter forward currents before and after reverse stress on the emitter-base junction. We show the influence of the chemical treatment preceeding polysilicon emitter deposition on noise properties. We identified that RTS noise arises from different regions in the device : the silicon/polysilicon interface if an oxidizing surface preparation is used, and the emitter periphery after stress-induced degradation. Temperature and bias dependent measurements allowed us to characterize these defects (activation energy, defect type), to analyse their impact to the low frequency noise properties of these transistors and to discuss the role of hot carrier stressing.     

Silicon planar epitaxial transistors as fast and reliable low-level switches

This paper attempts to accentuate all the salient factors of high-quality switches, such as their static properties, stability under various conditions of high temperature or thermal cycling, and some aspects of their transient response. It is shown that the silicon planar epitaxial transistor possesses the most advantageous combination of properites for general application as a low-level switch, and that simple low-injection level formulas are sufficiently accurate for the calculation of voltage offset and resistance of an "on" switch, as well as the "off" resistance, if extrinsic parameters and current dependence of βnand βiare taken into account. A simplified procedure is proposed for the selection of temperature-compensated switch pairs. Hysteresis in a single parameter βnis shown to be the main cause of instability in voltage offset in germanium alloy-type transistors, an effect which is hardly detectable in silicon planar epitaxial devices. Suitability of the latter for fast operation in chopper amplifiers is discussed, and their capabilities in a rapid-sampling commutator is illustrated.     

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF₂ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G_b) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h_fe) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h_fe-V_A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h_fe≈1600, excellent collector current saturation characteristics, an Early Voltage of V_A≈10 V, h_fe-V_A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV_EBO≈9.6 V, and a cut-off frequency of f_t=17.8 GHz     

Application of selective epitaxial silicon and chemo-mechanicalpolishing to bipolar transistors

Successful demonstration of single-polysilicon bipolar transistors fabricated using selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is reported. The pedestal structure made possible by the SEG/CMP process combination results in significantly reduced extrinsic-base collector capacitance. Cut-off frequency (f_T) of devices with emitter stripe width of 1 μm, a base width of 110 nm, and a peak base doping of 3×10¹⁸ cm^-3 have been observed to improve from 16 GHz to 22 GHz when the extrinsic-base collector overlap is decreased from 1 μm to 0.2 μm. Leakage current, often a problem for SEG structures, has been reduced to 27 nA/cm² for the area component, and 10 nA/cm for the edge component, by (1) appropriate post-polish processing, including a high-temperature anneal and sacrificial oxidation, (2) aligning the device sidewalls along the 〈100〉 direction, and (3) the presence of the pedestal structure. Base-emitter junction nonideality in these transistors has also been investigated     

A comparison of etched-geometry and overgrown silicon permeable base transistors by two-dimensional numerical simulations

Etched-geometry and overgrown Si permeable base transistors (PBT's) are compared by using two-dimensional numerical simulations. Because of the asymmetry of the etched structure, two biasing conditions are possible (etched-collector and etched-emitter) and both are considered. The base-to-collector transfer characteristics of PBT devices have two regions of operation. At low base-to-emitter voltages, barrier-limited current flow is observed, The two-dimensional nature of the depletion region near the Schottky-contact base grating results in a smaller electron barrier and thus a larger collector current in the etched structures than in the overgrown structure. At high base-to-emitter bias levels, charge is limited from entering the base region of the etched-emitter structure and from leaving the base region of the etched-collector device. The resulting parasitic feedback effects lead to a deviation from the square-law behavior found in the collector characteristics of the overgrown PBT. Because of the absence of semiconductor material directly above the base grating lines in the etched devices, these structures have lower device capacitances. They also have smaller transconductances at high base-to-emitter voltages. The important consequence of this is that overgrown and etched structures have comparable predicted maximum values of the small-signal unity short-circuit current-gain frequency and maximum frequency of oscillation. Fabrication-related effects are discussed qualitatively and GaAs PBT operation is considered in light of the present simulations.     

Selective silicon epitaxial growth on a submicrometer WSi2 grating: Application to the permeable base transistor

We report the silicon epitaxial growth on top of a tungsten disilicide grating using a rapid thermal processing, low pressure chemical vapor deposition reactor. The epitaxial growth of silicon is shown to proceed two dimensionally from the Si surface without reaction with the underlying WSi₂ grid. Both lateral diffusion over WSi₂ of Si adsorbed species and vertical diffusion of Si through the silicide film are shown to occur with respective weight depending on the width of the WSi₂ lines. This allows silicon selective growth on patterned Si/WSi₂ structure for grating periodicity below 1 μm. Preliminary electrical measurements of the Si/WSi₂/Si overgrown permeable base transistor (PBT) thus fabricated are presented, showing current densities J_max of up to 6000 A/cm² and transconductancesg _m of 5 mS/mm.     

HCl-free selective epitaxial Si-Ge growth by LPCVD forhigh-frequency HBTs

Low-temperature HCl-free selective silicon germanium epitaxial growth using low-pressure chemical vapor deposition was developed. By utilizing the incubation period of the poly-SiGe growth on SiO₂ , sufficient selectivity was obtained without the use of HCl gas. The advantages of this HCl-free process are sufficient growth rate at low temperature (660°C) and capability of high-concentration boron doping without surface roughening. The thickness uniformity of the selectively grown layers throughout a wafer was good and the local loading effect did not appear. These results show the process can be used for fabricating heterojunction bipolar transistors (HBTs). The HBTs fabricated using the process have excellent yields and high-frequency characteristics, that is, 80-GHz cutoff frequency and 160-GHz maximum oscillation frequency. These characteristics and good uniformity of cutoff frequency throughout a wafer show that developed selective growth process can be applied to production of SiGe HBTs     

High-performance SiGe epitaxial base bipolar transistors producedby a reduced-pressure CVD reactor

High-performance Si and SiGe epitaxial base bipolar transistors have been fabricated using a commercially available, reduced pressure, epitaxial reactor. The SiGe devices exhibit exceptional Early voltages in the range of 400-500 V, and an f_T of 31 GHz with a BV_CEO of 7.6 V and BV_CBO of 16 V. These results demonstrate that SiGe has potential as a commercially viable technology for analog, digital, and mixed-signal applications     

Pentacene thin film transistors fabricated by solution process with directional crystal growth

We have fabricated solution-processed pentacene thin film transistor arrays with mobilities as high as 1.0 cm²/V s, evaluated at a low drain voltage of ?10 V. This is achieved by controlling the growth direction of the pentacene films from solution, and by optimizing conditions for drop casting. Crystal growth of the solution-processed pentacene films is found to proceed in one direction on a tilted substrate. Grazing incidence X-ray diffraction and electron diffraction reveal that the crystal growth azimuth corresponds to the direction along the minor axis of the a–b plane in the unit cell of the pentacene crystal. This directional growth method is extended to solution processing on large glass substrates with an area of 150 × 150 mm², thereby yielding transistor arrays with two-dimensional uniformity and high carrier mobility.     

采用深槽刻蚀和外延生长技术的700V超结MOSFETs

超结理论的提出是功率器件领域发展的重要里程碑。基于HHNEC的工艺平台,采用深槽刻蚀和外延生长技术,得到了击穿电压大于700V的超结功率MOSFETs,实验值和仿真值吻合好。结果表明,所研制的超结功率MOSFETs,动态特性,特别是二极管的特性,优于国外同类型产品。该种结构的实验成功,打破了国内在该领域实用化研究的空白。     

Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth,based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited.The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation.The dynamic characteristics,especially reverse diode characteristics,are equivalent or even superior to foreign counterparts.     

Laser recrystallised SOI with periodical seeding filled by selective epitaxial growth

A periodic seeding technique for obtaining thin silicon films on an insulator (SOI) by laser recrystallisation is described. Two types of seed structure as well as their orientations relative to the scan direction are discussed. Geometrical parameters are optimised to obtain 35?m-wide defect-free SOI stripes across 4in (101-6mm) silicon wafers.     

Silicon variable capacitance diodes with high voltage sensitivity by low temperature epitaxial growth

Low temperature epitaxial vapor growth of silicon has been successfully applied to the fabrication of variable capacitance diodes which have a hyperabrupt impurity distribution profile. These diodes exhibit a strong nonlinear behavior in capacitance voltage characteristics; for example, one of the diodes has the value of n as high as 15 in the differential capacitance formula:dC/C = -n dV/(V + Phi). It has been found that the capacitance voltage and current voltage characteristics agree well with those calculated from the impurity profile so that the diodes with a high voltage sensitivity and with a high quality factor can be designed and fabricated reproducibly by this technique, and used in all solid-state FM modulators and automatic gain control units in a microwave relay system transmitting multiplex telephone signals. The double breakdown phenomenon in the current voltage characteristic of some diodes was observed and proved to be the saturation effect of generation recombination currents.     

Single-walled carbon nanotube transistors fabricated by advanced alignment techniques utilizing CVD growth and dielectrophoresis

Single-walled carbon nanotube field effect transistors (SWNT-FETs) are fabricated by two different alignment techniques. The first technique is based on direct synthesis of an aligned SWNTs array on quartz wafer using chemical vapor deposition. The transistor with three SWNTs and atomic layer deposited (ALD) Al₂O₃ gate oxide shows a contact resistance of 280 KΩ, a maximum on-current of ?7 μA, and a high I_on/I_off ratio (>10³). The second technique is based on room temperature self-assembly of SWNT bundles using dielectrophoresis. By applying AC electric fields, we have aligned nanotube bundles between drain and source contact patterns of a transistor at room temperature. Transistors based on twisted bundle of SWNTs show high contact resistance (MΩ range) and low current drive in the order of tens of nA.     

Growth condition dependence for GaAs selective epitaxial growth by molecular beam epitaxy

GaAs selective epitaxial growth by conventional molecular beam epitaxy (MBE) was studied while varying its growth conditions, such as substrate temperature. As pressure, growth rate, and Si or Be doping. Selectivity is improved with the increase in substrate temperature, and with the decrease in As pressure or growth rate. Si and Be were doped up to 3 x 10¹⁸ and 3 × 10¹⁹ cm⁻³, respectively. While no Si doping influence was observed, Be doping degraded the surface morphology. Selective epitaxial growth by conventional MBE with appropriate growth conditions will be applicable to device fabrication.