Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb/sub 2/O/sub 5/) with HfO/sub 2//Al/sub 2/O/sub 3/ barriers

A high capacitance density (C/sub density/) metal-insulator-metal (MIM) capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) whose k value is higher than 40, is developed for integrated RF bypass or decoupling capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a high C/sub density/ of >17 fF//spl mu/m/sup 2/ with excellent RF properties, while maintaining comparable leakage current and reliability properties with other high-k dielectrics. The capacitance from the dielectric is shown to be stable up to 20 GHz, and resonant frequency of 4.2 GHz and Q of 50 (at 1 GHz) is demonstrated when the capacitor is integrated using Cu-BEOL process.     

A new metal-ferroelectric (PbZr/sub 0.53/Ti/sub 0.47/O/sub 3/)-insulator (Dy/sub 2/O/sub 3/)-semiconductor (MFIS) FET for nonvolatile memory applications

Metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistors with Pb(Zr/sub 0.53/,Ti/sub 0.47/)O/sub 3/ ferroelectric layer and dysprosium oxide Dy/sub 2/O/sub 3/ insulator layer were fabricated. The out-diffusion of atoms between Dy/sub 2/O/sub 3/ and silicon was examined by secondary ion mass spectrometry profiles. The size of the memory windows was investigated. The memory windows measured from capacitance-voltage curves of MFIS capacitors and I/sub DS/-V/sub GS/ curves of MFIS transistors are consistent. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. A high driving current of 9 /spl mu/A//spl mu/m was obtained even for long-channel devices with a channel length of 20 /spl mu/m. The electron mobility is 181 cm/sup 2//V/spl middot/s. The retention properties of MFIS transistors were also measured.     

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

CO/sub 2/ laser processing of alumina (Al/sub 2/O/sub 3/) printed circuit board substrates

We report the results of an investigation of the laser-material interaction processes involved in laser drilling of alumina, through the use of an enhanced peak power (2.5 kW) CO/sub 2/ laser and novel temporal pulse formats. Peak power was varied from 30 W to 2 kW for pulses of constant energy to observe the effect produced on scribe depth. High-speed videography of hole formation has been combined with microscopic analysis to investigate the key processes involved in laser processing of alumina. Plasma screening was observed for short, high peak power laser pulses, and optimal scribing was achieved in the weakly plasma absorbing regime. A new processing technique for scribing alumina has been developed, which exploits the fast response of the laser to produce novel temporal pulse shapes, which can be modified to generate cleaner holes. Scribe speeds of up to 280 mm/spl middot/s/sup -1/ were obtained for scribe holes >200 /spl mu/m deep and 150 /spl mu/m apart, with no material plugging the hole, in 0.635-mm-thick 96% alumina.     

Threshold voltage (V/sub th/) instability in HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate: comparison between NH/sub 3/ and O/sub 3/ interface treatments

The impacts of O/sub 3/ or NH/sub 3/ interface treatments on the long-term V/sub th/ instability in nMOSFET HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate electrodes are compared. The NH/sub 3/ interface treatment is found to be beneficial to suppress the V/sub th/ shift compared to the O/sub 3/-treated samples. This is explained by an enhanced valence band electrons injection in O/sub 3/-treated samples and is experimentally confirmed through a carrier separation measurement. The dynamic stress measurement also indicates that trapped charges are more easily detrapped in NH/sub 3/-treated samples than O/sub 3/-treated samples, improving significantly the V/sub th/ stability.     

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

The performance of aggressively scaled (1.4nm相似文献   

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

Very high density RF MIM capacitors (17 fF//spl mu/m/sup 2/) using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectrics

Using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectric, we have obtained record high MIM capacitance density of 17 fF//spl mu/m/sup 2/ at 100 kHz, small 5% capacitance reduction to RF frequency range, and low leakage current density of 8.9/spl times/10/sup -7/ A/cm/sup 2/. In combination of both high capacitor density and low leakage current density, a very low leakage current of 5.2/spl times/10/sup -12/ A is calculated for a typical large 10 pF capacitor used in RF IC that is even smaller than that of a deep sub-/spl mu/m MOSFET. This very high capacitance density with good MIM capacitor characteristics can significantly reduce the chip size of RF ICs.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Effect of Thin-Film Bi/sub 2/O/sub 3/ Overlay on the Quality Factor of a Microstrip Resonator (Short Papers)

The effect of thin-film Bi/sub 2/O/sub 3/ overlay on a microstrip resonator has been studied. An improvement in Q suggests that Iower radiation loss may be achieved in this manner.     

High electron mobility 18300 cm2/V·s in the InAIAs/lnGaAs pseudomorphic structure obtained by channel indium composition modulation

The highest electron mobility yet reported for an InP-based pseudomorphic structure at room temperature, 18300 cm²/V·s, has been obtained by using a structure with an indium composition modulated channel, namely, In_0.53Ga_0.47As/ In_0.8Ga_0.2As/InAs/In_0.8Ga_0.2As/In_0.53Ga_0.47As. Although the total thickness of the high In-content layers (In_0.8Ga_0.2As/InAs/In_0.8Ga_0.2As) exceeds the critical thick-ness predicted by Matthews theory, In_0.8Ga_0.2As insertion makes it possible to form smooth In_0.53Ga_0.47As/In_0.8Ga_0.2As and In_0.8Ga_0.2As/InAs heterointerfaces. This structure can successfully enhance carrier confinement in the high In-content layers. This superior carrier confinement can be expected to lead to the highest yet reported electron mobility.     

Studies of CW laser oscillation on the 1315-nm transition of atomic iodine pumped by O/sub 2/(a/sup 1//spl Delta/) produced in an electric discharge

In this paper, we report on studies of a continuous-wave laser at 1315 nm on the I(/sup 2/P/sub 1/2/)/spl rarr/I(/sup 2/P/sub 3/2/) transition of atomic iodine where the O/sub 2/(a/sup 1//spl Delta/) used to pump the iodine was produced by a radio frequency excited electric discharge. The electric discharge was sustained in He-O/sub 2/ and Ar-O/sub 2/ gas mixtures upstream of a supersonic cavity which is employed to lower the temperature of the continuous gas flow and shift the equilibrium of atomic iodine in favor of the I(/sup 2/P/sub 1/2/) state. The results of experimental studies for several different flow conditions, discharge arrangements, and mirror sets are presented. The highest laser output power obtained in these experiments was 520 mW in a stable cavity composed of two 99.995% reflective mirrors.     

Path to the measurement of positive gain on the 1315-nm transition of atomic iodine pumped by O/sub 2/(a/sup 1//spl Delta/) produced in an electric discharge

Laser action at 1315 nm on the I(/sup 2/P/sub 1/2/)/spl rarr/I(/sup 2/P/sub 3/2/) transition of atomic iodine is conventionally obtained by a near-resonant energy transfer from O/sub 2/(a/sup 1//spl Delta/) which is produced using wet-solution chemistry. The system difficulties of chemically producing O/sub 2/(a/sup 1//spl Delta/) have motivated investigations into gas phase methods to produce O/sub 2/(a/sup 1//spl Delta/) using low-pressure electric discharges. We report on the path that led to the measurement of positive gain on the 1315-nm transition of atomic iodine where the O/sub 2/(a/sup 1//spl Delta/) was produced in a flowing electric discharge. Atomic oxygen was found to play both positive and deleterious roles in this system, and as such the excess atomic oxygen was scavenged by NO/sub 2/ to minimize the deleterious effects. The discharge production of O/sub 2/(a/sup 1//spl Delta/) was enhanced by the addition of a small proportion of NO to lower the ionization threshold of the gas mixture. The electric discharge was upstream of a continuously flowing supersonic cavity, which was employed to lower the temperature of the flow and shift the equilibrium of atomic iodine more in favor of the I(/sup 2/P/sub 1/2/) state. A tunable diode laser system capable of scanning the entire line shape of the (3,4) hyperfine transition of iodine provided the gain measurements.     

Modeling the effect of thin gate insulators (SiO2, SiN,Al2O3 and HfO2) on AlGaN/GaN HEMT forward characteristics grown on Si,sapphire and SiC

GaN-based high electron mobility transistors (HEMTs) with a Schottky metal gate have been demonstrated to be an excellent candidate for high frequency, high temperature and high power applications. Nevertheless, their typical (and virtually inevitable) high gate leakage current, severely limits gate voltage swing, output power and breakdown voltage. GaN metal–insulator –semiconductor HEMTs or MIS-HEMTs (formed by introducing a thin dielectric film between the gate metal and semiconductor) is one of the effective solutions that reduce gate leakage and improve device performance. In this work, we evaluate the effect that the introduction of this gate insulator has on the on-state of the HEMT. For this reason, we develop a complete set of compact closed-form expressions for the evaluation of on-resistance, drain and saturation current and transconductance for a MIS-HEMT. This physical-based model describes the mobility in a 2D electron gas channel by means of optical phonon scattering and is explored with insulators based on SiO₂, SiN_x, Al₂O₃, and HfO₂.     

Potential gain in photocurrent generation for Cu(In,Ga)Se2 solar cells by using In2O3 as a transparent conductive oxide layer

This study highlights the potential of atomic layer deposited In₂O₃ as a highly transparent and conductive oxide (TCO) layer in Cu(In,Ga)Se₂ (CIGSe) solar cells. It is shown that the efficiency of solar cells which use Zn‐Sn‐O (ZTO) as an alternative buffer layer can be increased by employing In₂O₃ as a TCO because of a reduction of the parasitic absorption in the window layer structure, resulting in 1.7 mA/cm² gain in short circuit current density (J_sc). In contrast, a degradation of device properties is observed if the In₂O₃ TCO is combined with the conventional CdS buffer layer. The estimated improvement for large‐scale modules is discussed. Copyright © 2015 John Wiley & Sons, Ltd.