A low-power BiCMOS switched-capacitor filter for audio codecapplications

A fully integrated fourth-order filter embedded in a complete 16-b oversampled D/A converter to be used in an audio stereo codec is presented. The possible noise and distortion sources have been accurately evaluated in the design and their contributions have been properly limited. This allows the reduction of the power consumption while satisfying the application requirements. The filter is realized in 0.7-μm BiCMOS technology with an active area of about 1.3 mm² . A total harmonic distortion (THD) of -75 dB for a full scale input signal and an SNR of 96 dB have been achieved. The power consumption of the filter has been maintained within about 40 mW from a single 5-V supply voltage     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

Chemical log-domain filter

Presented is a chemical log-domain filter in which an ion sensitive field effect transistor (ISFET) is used to expand a naturally log-compressed chemical signal to derive a chemically-dependent lossy-integrator, whose gain and bandwidth are functions of ion concentration. This is used to integrate small chemical signals or have a filter adaptable to changes in chemical concentration.     

A novel first-order log-domain allpass filter

This paper proposes a first-order allpass log-domain filter, which is systematically derived using the state-space synthesis procedure. To the best knowledge of the authors, the filter is the first log-domain first-order allpass filter in the literature. The proposed filter has a simple structure and can be electronically tuned. PSPICE simulations are given to confirm the theoretical analysis.     

A BiCMOS low-power current mode gate

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML     

A low-power and compact CDMA matched filter based on switched-current technology

A low-power and compact code-division multiple-access (CDMA) matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture, which reduced the current flowing in current-memory cells. A low-power clock-on-demand shift register has also been developed. The 256-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated the power dissipation of 1.95 mW at the chip rate of 8 Mchip/s under 2-V power supply. The chip occupies the area of 0.54 mm/sup 2/.     

Table-based log-domain linear transformation filter

A design table for realising log-domain linear transformation filters is presented. Based on this design table, doubly terminated LC ladder filters with or without finite transmission zeros can be efficiently synthesised. Moreover, two design procedures are also given. A canonical log-domain elliptic ladder filter can be realised using one of these procedures. Simulation results are given to verify the theoretical analysis     

A high-performance, low-power complementary coupled BiCMOS circuit

Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits     

规范正交梯形结构对数域滤波器

提出了一种基于规范正交梯形网络信号流图模拟的对数域滤波器设计方法.能直接对给定的任意高阶传输函数进行综合.用该方法设计了1dB波纹三阶椭圆埘数域低通滤波器.Pspice仿真表明,所设计的滤波器实际频响特性几乎是理想的,而且具有电路结构简单、需要的元件数少、灵敏度低和最优的动态范围等特性.     

A compact low-power UHF RFID tag

In this paper, the design of an ultra-low-power UHF RFID tag is introduced. The system architecture and the communication protocols are chosen to operate with the minimum requirements possible from the RFID tag. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13 μm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1 μW, and the chip area is only 0.14 mm×0.23 mm.     

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

A micropower class-AB CMOS log-domain filter for DECT applications

This paper presents a micropower second-order low-pass filter using the log-domain principle and integrated in a 0.35-μm CMOS process. It has been designed as an antialiasing filter for a DECT transceiver with a 45-kHz nominal cutoff frequency. The circuit uses transistors biased in weak inversion without requiring separate wells. It operates at 1.5-V supply voltage and its current consumption is 8 μA in idle mode. The log-domain filter is implemented with an on-chip conditioner which allows class-AB operation. It can process input currents at 5 kHz that are 25 times larger than the 200-nA bias current. Measurements up to 500 times the bias current have been done, since at 1 kHz the input current is only limited by the supply voltage     

Micropower log-domain filter for electronic cochlea

A new approach to the design of a low-power cascadable analogue filter for applications such as silicon cochlea implants is described. One section of a possible silicon cochlea based on a second-order continuous-time filter employing MOS technology operating in weak inversion is presented. The idea is based on the recently proposed log-domain filter approach used previously in bipolar technology     

Unifying perspective on log-domain filter synthesis

A unifying framework is presented for the in-depth understanding of the seemingly unrelated state-space-based and translinear methods proposed for the synthesis of externally linear but internally nonlinear logdomain filters. The translinear methods exploit either the 'dynamic translinear principle' or the Bernoulli Cell dynamics. Light is shed in an insightful manner on key interconnections between Frey's nodal state-space-based synthesis relations, translinear loop-based synthesis conditions and the archetypal linear filter dynamics by considering the form of the state variables used in each case.     

A low-power high-gain transresistance BiCMOS pulse amplifier forcapacitive detector readout

A low-power, high-gain amplifier for detector readout is discussed. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields in the large detector. Before irradiation, the circuit has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time t_10/90% of 19 ns, a noise figure of 433⊕93·(C_t)^1.08 electrons, e^-, and a power consumption of 750 μW. To keep the core amplifier stable, a low-power super-low gain-bandwidth (SL-GBW) amplifier with a small area is used and also discussed. The SL-GBW amplified has a transition frequency f_T of 38 kHz (including the gain stage, A), a power consumption of 150 nW, a phase margin (PM) of ≈70°, an area of 300×36 μm², and a minimum current per transistor of 7 nA, which is far above the leakage current after irradiation. The complete circuit was implemented in the radiation hard SOI-SIMOX BiCMOS-PJFET technology of DMILL     

一种高速低功耗BiCMOS脉冲式触发器的通用结构

BiCMOS电路兼具CMOS电路高集成度,低功耗的优点和双极型电路高速大驱动能力的优势,已成为目前国际学术界研究的热点之一。本文提出了一种基于BiCMOS工艺的新型脉冲式触发器的通用结构和设计方法,并设计了两种结构简单的BiCMOS脉冲式D型触发器。应用TSMC 180nm工艺,采用HSPICE模拟表明:所设计的BiCMOS脉冲式D型触发器不仅具有正确的逻辑功能,而且具有高速低功耗大驱动能力的优点,与已有文献提出的BiCMOS D型触发器相比,功耗和PDP均有大幅度降低。     

Multiband monolithic BiCMOS low-power low-IF WLAN receivers

This letter presents the design, implementation, and measurements of two monolithic low-IF receivers compliant with the main WLAN standards. The first receiver targets the three 5GHz U-NII bands, while the second allows dual-band operation in the 2GHz and 5GHz bands. Fabricated in a 47GHz-f/sub t/ BiCMOS technology, both consist of a low-noise preamplifier, two matched active singly-balanced mixers and two polyphase filters, used to generate quadrature LO signals and provide image-rejection. The single-band receiver exhibits 25 dB of conversion gain, 8.9 dB of NF and -19 dBm of P/sub 1 dB/, while consuming 19 mW. The dual-band receiver shows similar performances in the 5GHz band, and extends its operation in the 2GHz band, achieving 33.4dB of conversion gain, 4.1dB of NF and -26dBm of P/sub 1 dB/, while consuming 14.9mW.     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation     

A BiCMOS low-distortion 8-MHz low-pass filter

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2-μm 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than ±1 dB over a 100°C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V_pp, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V_pp inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc