一种单环5阶高精度音频△-∑ A/D转换器

采用英飞凌0.11 μm CMOS工艺,实现了一种用于音频范围的高精度△-∑ A/D转换器.调制器采用1位量化的5阶单环前馈结构,ADC过采样率为256.A/D转换器模拟调制器工作于5V电压,数字滤波器工作于1.2V电压,整体功耗为20.52 mW,版图面积3.1 mm2.仿真结果显示,设计的A/D转换器在20 kHz信号带宽内达到108.9 dB的信噪失真比,有效位数为18位.     

一种稳定的高阶∑—△模／数转换器

文章提出了一种稳定的高阶∑-△模数转换器的设计方法。结合实例，简要说明了多级数字抽取滤波器的设计，并讨论了调制器基内零点优化的方法。设计的∑-△A/D转换器可以满足无线通信应用中大动态范围A/D转换的要求。     

用于过采样Σ-△ A/D转换器的Σ-△调制器

分析并讨论了过采样∑-△A/D转换器中一阶、二阶及高阶级联结构的∑-△调制器的性能特点,并编写C语言程序进行行为级仿真,用PSpice进行电路级仿真,利用MATLAB工具对其结果进行分析.结果表明,∑-△调制器具有噪声整形特性,可以提高基带内的信噪比,且三阶级联结构中1-1-1结构性能最优.∑-△调制器与过采样技术相结合可构成高精度、低成本的A/D转换器.     

A 16 bit Stereo Audio ΣΔ A/D Converter

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

一种16位音频∑△ A/D转换器

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

一种高精度∑-ΔA/D转换器的数字滤波器设计

设计了一种用于高精度音频∑-ΔA/D转换器的数字滤波器.该滤波器由级联梳状滤波器(CIC)、补偿滤波器和半带滤波器组成.设计中采用了乘法器分时复用技术以减少电路面积.设计的滤波器可实现128/64两种抽取率,其性能可满足该∑-ΔA/D转换器的要求.     

一种0.35 μm CMOS高精度Σ-Δ A/D转换器

提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。     

Σ-Δ模数转换器工作原理及简单分析

∑-ΔA/D转换器是一种高精度的模数转换器,它和传统的A/D转换器不同,具有高分辨率、高集成度、造价低和使用方便的特点,并且越来越广泛地使用在一些高精度仪器仪表和测量设备中。文章从信号的过采样、噪声整形、数字抽取滤波等方面分析了∑-ΔA/D转换器的工作原理,对人们全面了解∑-ΔA/D转换器有一定的帮助。     

14-b 400-ksps 2.5-mW连续时间∑-Δ调制器

连续时间∑-△调制器较之传统的开关电容∑-△调制器具有更低的功耗、更小的面积,以及集成抗混叠滤波器等诸多优势.设计了一种应用于低中频GSM接收机的4阶单环单比特结构的连续时间∑-△调制器.在调制器中,采用了开关电容D/A转换器,以降低时钟抖动对性能的影响.仿真结果显示,在1.8 V工作电压、200 kHz信号带宽、0.18 μm CMOS工艺条件下,采样频率21 MHz,动态范围(DR)超过90 dB,功耗不超过2.5 mW.     

一种用于过采样∑-△ A／D转换器的抽取滤波器

采用0．8μm CMOS工艺，实现了一种用于过采样∑-△ A／D转换器的数字抽取滤波器。该滤波器采用多级结构，梳状滤波器作为首级，用最佳一致逼近算法设计的FIR滤波器作为末级，并通过位串行算法硬件实现。芯片测试表明，该滤波器对128倍过采样率、2阶∑-△调制器的输出码流进行处理得到的信噪比为75dB。     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process     

一款高速、低功耗的Sigma-Delta模数转换器

提出了一种高速、低功耗、高分辨率的新型Sigma-Delta模数转换器(ADC)结构。该结构选择过采样率(OSR)为32的4阶调制器设计以缓解输出速率和通带宽度的压力,采用级联和双量化的方法进行优化,并利用SIMSIDES工具(基于Simulink的Sigma-Delta仿真器)进行仿真。数字抽取滤波器部分由级联积分梳状(CIC)滤波器、有限长单位冲激响应(FIR)滤波器和半带(HB)滤波器组成,并且三级滤波器都采用了多相分解结构,以降低动态功耗。使用0.18μm的标准CMOS工艺实现数字抽取滤波器版图。仿真结果表明,在250 kHz带宽下,有效位宽(ENOB)为19 bit。     

12位Sigma-Delta模数转换器的降采样滤波器设计

一种由SNR（信噪比）驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位Sigma-Delta模数转换器的要求。     

Double‐Sharpened Decimation Filter Employing a Pre‐droop Compensator for Multistandard Wireless Applications

This paper presents a double‐sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double‐sharpened decimation filter uses a pre‐droop compensator which improves the passband response of a conventional cascaded integrator‐comb filter so that it provides an efficient sharpening performance at half‐speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides –1.6 dB for 1.25 MHz, –1.4 dB for 2.5 MHz, –1.3 dB for 5 MHz, and –1.0 dB for 10 MHz bandwidths, respectively. These results demonstrate that the proposed double‐sharpened decimation filter is suitable for multistandard wireless applications.     

A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process     

A monolithic ΣΔ A/D and D/A converter with filter forbroad-band speech coding

The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analog/digital (A/D) and digital/analog (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filters for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm² die in a 3-μm SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade     

A high-performance,low-power ∑Δ ADC for digital audio applications

A high-performance low-power ∑Δ analog-to-digital converter (ADC) for digital audio applications is described.It consists of a 2-1 cascaded ∑Δ modulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficientoptimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2,which dissipates only 2.1 mA quiescent current in the analog circuits.     

Integrated switched-capacitor low-pass filter with combined anti-aliasing decimation filter for low frequencies

A new combined antialiasing decimation filter is presented which allows the implementation of a low-frequency switched-capacitor filter on a single chip. Experimental results are presented for a CMOS second-order low-pass filter with 1 dB passband ripple, a cutoff frequency of 2 Hz, and a dynamic range of 84 dB. The decimation filter converts the input clock of 16 kHz into an output clock of 250 Hz. The integrated anti-aliasing filter has a low pole frequency of about 3 kHz.     

一种宽带多模数字抽取滤波器

提出了一种应用于连续时间Σ-Δ ADC的多模数字抽取滤波器。通过采用不同类型滤波器级联结构,合理分配不同级间下采样因子,有效降低了电路复杂度、面积和功耗。通过级间滤波器相互配合,实现了该滤波器的多带宽、多模式功能。基于65 nm CMOS工艺进行后端设计,仿真结果表明,该多模抽取滤波器的工作带宽为20~50 MHz,当工作带宽为20 MHz和50 MHz时,有效位数分别为10.64位和10.48位。