Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.     

Solder joint reliability and characteristics of deformation and crack growth of Sn-Ag-Cu versus eutectic Sn-Pb on a WLP in a thermal cycling test

Sn-Ag-Cu (SAC) is now recognized as the standard lead free solder alloy for packaging interconnect in the electronics industry. This paper analyzes the performance of both SAC and eutectic Sn-Pb solder alloys on Kulicke & Soffa's (K&S') Ultra CSP/spl reg/ wafer level package (WLP) at a thermal cycling (TC) test. The Ultra CSP standard Al/Ni-V/Cu under bump metallurgy (UBM) system was used to analyze if this UBM system with SAC solder would produce acceptable reliability in the TC test. In this study, two TC tests were performed. In the first test, two parts were removed from the TC chamber about every 200 cycles to investigate the characteristics of deformation and crack growth in the SAC and eutectic Sn-Pb Ultra CSP solder joints during TC testing. These TC test results showed that both the SAC and eutectic Sn-Pb Ultra CSPs exhibited normal solder joint fatigue failures during the testing. The SAC Ultra CSP had an equal or 18% higher Weibull life than the eutectic Sn-Pb one. Based on these results it was concluded that the SAC Ultra CSP with the Al/Ni-V/Cu UBM system produces acceptable solder joint reliability in a TC test. The results also revealed that the deformation and crack growth characteristics of the SAC and eutectic Sn-Pb Ultra CSP solder joints were significantly different. The eutectic Sn-Pb solder joints showed significant inelastic shear deformation during the TC testing while the SAC solder joints did not display significant inelastic deformation even at the high temperature regime of the TC test.     

Joint reliability of various Pb-free solders under harsh vibration conditions for automotive electronics

These days, realization of technology for automotive electronics is important for convenience and safety in automobile industries. Although technology development is continuously progressing, various problems associated with the reliability of automotive electronics have arisen. In this study, combined vibration tests were performed to determine the reliability of various solders under harsh environments: Sn-3.0Ag-0.5Cu (SAC305), Sn0.7Cu and Sn-0.5Cu-0.01Al-0.005Si-0.008Ge (SnCuAl(Si)) solder (in wt%). The Pb-free solder balls were used on electroplating nickel finished Cu pads of a fine ball grid array (FBGA) package. The BGA packages mounted with solder balls were set up on electroless nickel-immersion gold (ENIG) finished Cu pads of a daisy-chained printed circuit board (PCB). The combined random vibration test was performed under 2.5 G_rms in the range of 400 to 2000 Hz in the temperature range of −45 to 125 °C and was continued until 500 cycles. The reliability of the solder joint was determined by measuring the electrical resistance using a multi-meter. The resistance gradually increased and finally approached infinity. In addition, the IMC thicknesses increased during the combined random vibration test, which affected the fracture behavior. To determine the reliability of the solders, the number of failures of solders and the crack morphology and propagation in each solder were evaluated. Among the three solders, the SnCuAl(Si) solder demonstrated the best reliability.     

Comparative study of micro-BGA reliability under bending stress

The micro-ball grid array (/spl mu/BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by ordinary surface mount technology. In the latest /spl mu/BGA type, eutectic tin-lead solder ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the /spl mu/BGA's PCB, which is soldered by conventional surface mount technology, has been studied in this paper. The bending cycle test (1000 /spl mu//spl epsi/ to -1000 /spl mu//spl epsi/), is used to investigate the fatigue failure of solder joints of /spl mu/BGA, PBGA, and CBGA packages reflowed with different heating factors (Q/sub /spl eta//), defined as the integral of the measured temperature over the dwell time above liquidus (183/spl deg/C). The fatigue lifetime of the /spl mu/BGA assemblies firstly increases and then decreases with increasing heating factor. The greatest lifetime happens while Q/sub /spl eta// is near 500 second-degree. The optimal Q/sub n/ range is between 300 and 750 s/spl deg/C. In this range, the lifetime of the /spl mu/BGA assembly is greater than 4500 cycles if the assemblies are reflowed in nitrogen ambient. SEM micrographs reveal that both /spl mu/ & P-BGA assemblies fail in the solder joint at all heating factors. All fractures are near and parallel to the PCB pad. In the /spl mu/BGA assemblies cracks always initiate at the point of the acute angle where the solder joint joins the PCB pad, and then propagate in the section between the Ni/sub 3/Sn/sub 4/ intermetallic compound (IMC) layer and the bulk solder. In the CBGA assembly reliability test, the failures are in the form of delamination, at the interface between the ceramic base and metallization pad.     

Chip scale package issues

Availability of board solder joint reliability information is critical to the wider implementation of chip scale packages (CSPs). The JPL-led CSP consortia of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of CSPs for variety of projects. In the process of building the consortia test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of CSP test vehicles.     

Impact of 5% NaCl Salt Spray Pretreatment on the Long-Term Reliability of Wafer-Level Packages with Sn-Pb and Sn-Ag-Cu Solder Interconnects

Understanding the sensitivity of Pb-free solder joint reliability to various environmental conditions, such as corrosive gases, low temperatures, and high-humidity environments, is a critical topic in the deployment of Pb-free products in various markets and applications. The work reported herein concerns the impact of a marine environment on Sn-Pb and Sn-Ag-Cu interconnects. Both Sn-Pb and Sn-Ag-Cu solder alloy wafer-level packages, with and without pretreatment by 5% NaCl salt spray, were thermally cycled to failure. The salt spray test did not reduce the characteristic lifetime of the Sn-Pb solder joints, but it did reduce the lifetime of the Sn-Ag-Cu solder joints by over 43%. Although both materials showed strong resistance to corrosion, the localized nature of the corroded area at critical locations in the solder joint caused significant degradation in the Sn-Ag-Cu solder joints. The mechanisms leading to these results as well as the extent, microstructural evolution, and dependency of the solder alloy degradation are discussed.     

Microstructural Analysis of Reballed Tin-Lead,Lead-Free,and Mixed Ball Grid Array Assemblies Under Temperature Cycling Test

In this study, ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (SAC305) solder balls were reballed with Sn-37Pb solder balls. Three different reballing methods were used. The non-reballed lead-free BGAs were assembled with SAC305 and Sn-37Pb solder pastes to form the lead-free and mixed assemblies. The reballed Sn-Pb BGAs were assembled with Sn-37Pb solder paste to form the reballed Sn-Pb assemblies. All assemblies were subjected to a temperature cycling test with a temperature range of −55°C to 125°C. For the same component type, the reballed BGA assemblies showed similar temperature cycling reliability regardless of the reballing methods. However, the temperature cycling reliability of the reballed assemblies was worse than that of the mixed and the lead-free assemblies. The mean cycles-to-failure of the mixed assemblies was larger than or equal to that of the lead-free assemblies. Failure analysis revealed that the failure site in reballed Sn-Pb assemblies was located in the bulk solder at the component side regardless of the component type and the reballing method, indicating that the reballing method did not influence the crack propagation in reballed assemblies. The mixed assemblies had the same failure site as the lead-free assemblies, i.e., in the bulk solder at the component side. The microstructure differences between the tin-lead, lead-free, and mixed assemblies are also discussed in detail.     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Effect of Gold Content on the Microstructural Evolution of SAC305 Solder Joints Under Isothermal Aging

Au over Ni on Cu is a widely used printed circuit board (PCB) surface finish, under bump metallization (UBM), and component lead metallization. It is generally accepted that less than 3 wt.% Au in Sn-Pb solder joints inhibits formation of detrimental intermetallic compounds (IMC). However, the critical limit for Au content in Pb-free solder joints is not well established. Three surface-mount package platforms, one with a matte Sn surface finish and the others with Ni/Au finish, were soldered to Ni/Au-finished PCB using Sn-3.0Ag-0.5Cu (SAC305) solder, in a realistic manufacturing setting. The assembled boards were divided into three groups: one without any thermal treatment, one subjected to isothermal aging at 125°C for 30 days, and the third group aged at 125°C for 56 days. Representative solder joints were cross-sectioned and analyzed using scanning electron microscopy (SEM) and energy-dispersive x-ray spectroscopy (EDX) to investigate the evolution of the solder joint morphology as a function of Au content and isothermal aging. It was found that, if Cu is available to dissolve in the solder joint, the migration of AuSn₄ from the bulk to the interface as a result of thermal aging is mitigated.     

Design and analysis of wafer-level CSP with a double-pad structure

Wafer level chip scale packaging (WLCSP) is very promising for the miniature of packaging size, the reduction of manufacturing cost, and the enhancement of the package's performance. However, the long-term board level reliability of integrated circuit (IC) devices using wafer level packaging with large distances from neutral point (DNP) is still not fully solved. This research proposes a novel, alternative WLCSP design for facilitating higher board level reliability. The main feature of the novel WLCSP is basically in its double-pad structure (DPS) design in the interface between solder joints and silicon chip. To characterize the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear finite element (FE) modeling technique is employed. Based on the FE modeling, the numerical accelerated thermal cycling (ATC) test is performed under the JEDEC temperature cycling specification. The validity of the proposed FE modeling is verified by using an optical measurement method Twyman-Green interferometer. By the derived incremental equivalent plastic strain, the cumulative cycles to failure in solder joints associated with these four WLCSP are assessed based on a modified Coffin-Manson relationship. The modeled fatigue life is compared against the experimental results that adopt a two-parameter Weibull distribution to characterize cycles-to-failure distribution. For comparison, the investigation also involves several existing types of WLCSP, including the conventional (C-WLCSP), the copper post (CP-WLCSP), and the polymer post (PP-WLCSP), and solder joint reliability performance among these WLCSP packages is extensively compared. The results demonstrate that the DPS-WLCSP design not only has potential for enhancing the corresponding solder joint reliability but is also particularly effective in manufacturing process and cost. And finally, some reliability-enhanced design guidelines are provided through parametric design of the DPS.     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

The effect of modifications to the nickel/gold surface finish on assembly quality and attachment reliability of a plastic ball grid array (peer review version)

Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of standard and experimentally modified ENIG surface finishes. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.     

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

Drop impact reliability testing for lead-free and lead-based soldered IC packages

Board-level drop impact testing is a useful way to characterize the drop durability of the different soldered assemblies onto the printed circuit board (PCB). The characterization process is critical to the lead-free (Pb-free) solders that are replacing lead-based (Pb-based) solders. In this study, drop impact solder joint reliability for plastic ball grid array (PBGA), very-thin quad flat no-lead (VQFN) and plastic quad flat pack (PQFP) packages was investigated for Pb-based (62Sn–36Pb–2Ag) and Pb-free (Sn–4Ag–0.5Cu) soldered assemblies onto different PCB surface finishes of OSP (organic solderability preservative) and ENIG (electroless nickel immersion gold). The Pb-free solder joints on ENIG finish revealed weaker drop reliability performance than the OSP finish. The formation of the brittle intermetallic compound (IMC) Cu–Ni–Sn has led to detrimental interfacial fracture of the PBGA solder joints. For both Pb-based and Pb-free solders onto OSP coated copper pad, the formation of Cu₆Sn₅ IMC resulted in different failure sites and modes. The failures migrated to the PCB copper traces and resin layers instead. The VQFN package is the most resistant to drop impact failures due to its small size and weight. The compliant leads of the PQFP are more resistant to drop failures compared to the PBGA solder joints.     

Wafer level chip scale packaging (WL-CSP): an overview

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. Rambus^TM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages     

Effects of build-up printed circuit board thickness on the solderjoint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer     

Interfacial reaction study on a solder joint with Sn-4Ag-0.5Cu solder ball and Sn-7Zn-Al (30 ppm) solder paste in a lead-free wafer level chip scale package

The interfacial reactions of solder joints between the Sn-4Ag-0.5Cu solder ball and the Sn-7Zn-Al (30 ppm) presoldered paste were investigated in a wafer level chip scale package (WLCSP). After appropriate surface mount technology (SMT) reflow process on the printed circuit board (PCB) with organic solderability preservative (Cu/OSP) and Cu/Ni/Au surface finish, samples were subjected to 150°C high-temperature storage (HTS), 1,000 h aging. Sequentially, the cross-sectional analysis is scrutinized using a scanning electron microscope (SEM)/energy-dispersive spectrometer (EDS) and energy probe microanalysis (EPMA) to observe the metallurgical evolution in the interface and solder buck itself. It was found that Zn-enriched intermetallic compounds (IMCs) without Sn were formed and migrated from the presolder paste region into the solder after reflow and 150°C HTS test.     

Interfacial reactions in the pb-free composite solders with indium layers

A Pb-free composite solder is prepared with a Pb-free solder substrate and a plated-indium layer. The indium layer melts during the soldering process, wets the substrates, and forms a sound solder joint. Since the melting temperature of indium is 156.6°C, lower than that of the eutectic Sn-Pb, which is at 183°C, the soldering process can be carried out at a temperature lower than that of the conventional soldering process. Composite solder joints with three different Pb-free solders, Sn, Sn-3.5 wt.% Ag, and Sn-3.5 wt.% Ag-0.5 wt.% Cu, and two substrates, Ni and Cu, are prepared. The interfaces between the indium layer, Pb-free solder, and Ni and Cu substrate are examined. A good solder joint is formed after a 2-min reflow at 170°C. A very thick reaction zone at the indium/Pb-free solder interface and a thin reaction layer at the indium/substrate interface are observed.