Controlled two-step solid-phase crystallization forhigh-performance polysilicon TFT's

Solid-phase crystallization for polysilicon thin-film transistors (TFT's) is generally limited by a tradeoff between throughput and device performance. Larger grains require lower crystallization temperatures, and hence, longer crystallization times. In this letter, a novel crystallization technique is presented which increases both throughput and device performance, using a two-step process, controlled using an in situ acoustic temperature/crystallinity sensor. A high-temperature rapid thermal annealing (RTA) nucleation step is followed by a low-temperature grain growth step to grow large-grain polysilicon. TFT's have been fabricated with a substantial improvement in throughput and device performance. This promises a high-throughput, high-performance, spatially uniform TFT process     

A physical-based analytical turn-on model of polysilicon thin-filmtransistors for circuit simulation

A physical-based analytical current model of poly-Si thin film transistors (TFT's) for circuit simulation is presented. The model includes the barrier potential at grain boundaries, drain induced grain barrier lowering (DIGBL), temperature dependence, and the kink effect. The basic equation in the model has an analytic form for implementation in circuit simulators. The model has simple relationships between model parameters and device or material parameters. In addition to the current model, a capacitance model based on the current model is presented. Comparisons between the model and measured results show excellent agreement over wide ranges of operating voltages and for devices with different channel lengths     

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

The anomalous behavior of hydrogenated/unhydrogenated polysiliconthin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFT's) with/without plasma hydrogenation under the stress condition of V_ds=-15 V and V_gs=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFT's but not for hydrogenated TFT's. Also, the off-state current is deteriorated for unhydrogenated TFT's but, on the contrary, it is improved for hydrogenated TFT's. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFT's under electric stress     

Optimizing polysilicon thin-film transistor performance withchemical-mechanical polishing and hydrogenation

Chemical-mechanical polishing and hydrogen passivation were jointly used to improve the electrical characteristics of polycrystalline-Si thin-film transistors (poly-Si TFT's). It was found that each treatment affects the devices differently; polishing is more effective in smoothing the poly-Si/SiO₂ interface while hydrogenation is more effective in passivating the grain boundaries. Their effects are additive. Hence, optimal device performance was achieved by combining both treatments     

The thin film transistor—A late flowering bloom

The thin film transistor was the first solid-state amplifier ever patented, but has found no practical application until quite recently. The history of this device is traced from the early and unsuccessful Bell Labs experiments, through its brief resurgence in the 1960's as a competitor to the MOSFET; its second disappearance from public view followed by years of hibernation at Westinghouse Labs; its emergence in the 1970's as a candidate for forming very large area integrated circuits for flat panel displays, leading to the present era of intensive, worldwide exploitation as a device which has at last found a suitable problem to solve. The present state of the art of TFT's made of CdSe, poly- and amorphous silicon is reviewed, particularly as it pertains to their current predominant use in high resolution/high performance liquid crystal displays, followed by some views on the future for TFT's in active matrices and, possibly, in other "human size" or macro-electronic components and systems.     

Performance enhancement of offset gated polysilicon thin-film transistors

Simple offset gated n-channel polysilicon thin film transistors (TFTs) of channel length L=10 /spl mu/m were investigated in relation to the intrinsic offset length /spl Delta/L and the polysilicon quality. For /spl Delta/L/spl les/1 /spl mu/m, the device parameters such as threshold voltage, subthreshold slope and field effect mobility are improved, while the leakage current remains unchanged. In TFTs with /spl Delta/L>1 /spl mu/m, the leakage current decreases with increasing the offset length. When the polysilicon layer is of high quality (large grain size and low intra-grain defect density), the leakage current is completely suppressed without sacrificing the on-current in TFT's with offset length of 2 /spl mu/m.     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A statistical model to predict grain boundary distribution in the channel of a polysilicon thin-film transistor (TFT) is proposed. The model is valid for arbitrary transistor size to grain size ratio, and is particularly useful to predict the grain boundary distribution of recrystallized large-grain polysilicon TFTs where the transistor size is comparable to the grain size and gives significant device-to-device variation. The model has been extensively verified by comparing it with statistical data obtained from TFTs fabricated using metal-induced-lateral-crystallization and regular solid-phase epitaxial techniques. Good agreements between the experimental results and model prediction are demonstrated.     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

Influence of microstructural variation on the electrical propertiesof SiC microthermistors

The effects of the microstructural nonuniformity on the variations in the electrical properties of SiC ceramic were estimated quantitatively through simulations in order to produce microthermistors with the material. In these simulations, the grain size, the trap concentration at the grain boundary and the doping level in the grain were considered as the various microstructural nonuniformities. The device size was also taken into account as a parameter. The boundary potential model and the energy band model were used to express the electrical characteristics of the grain boundaries in the simulations. It is pointed out that those nonuniform microstructures greatly influence the electrical conductivity and the sensitivity of the SiC ceramic microthermistor. These phenomena are explained by the percolation theory. The tolerance of microstructural variation in the production of the ceramic is also discussed. It is revealed that the percolation threshold has the possibility to be used as an index of the acceptable microstructural tolerances     

Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

An analytical model for the above-threshold characteristics ofpolysilicon thin-film transistors

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E_c -0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias     

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively.These laser crystallized TFT's show poorer reliability properties than solid-phase crystallized TFT's. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations.Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV_T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFT's by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFT's where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).     

A large-bias conduction model of polycrystalline silicon films

There exists a need for a large-bias conduction model of polysilicon films used in VLSI/ULSI and in high power integrated circuits. A large-bias conduction model has been developed by extending the emission-based models of Lu et al. (1983) and Mandurah et al. (1981) valid for small-bias, small-signal conditions. The following large-bias effects have been taken into account: (1) asymmetry of potential distribution around grain boundaries and (2) avalanche multiplication of carriers in the grain boundary layers at high electric fields. Since the exact nature of the grain boundary material is not yet known, and there is no direct method for determining the model parameters relating to grain boundaries, these were extracted by the parametric fitting of resistance versus temperature data of polysilicon resistors near room temperature with the above small-signal resistivity models modified by including Fermi-Dirac distribution. The model has been validated with experimental data on the current-voltage characteristics of ion-beam sputtered polysilicon resistors of different sizes and aspect ratios. The dependence of model parameters relating to grain boundary scattering and avalanche multiplication on the dimensions of resistors have been explained physically. The increased kink effect in polysilicon TFT's may also be predicted from the present theory. Some results on the I-V characteristics of polyresistors trimmed by high current pulses have been discussed qualitatively in the light of the present model. Although the model involves numerical integrations and a few iterations, it is reasonably fast in execution     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's