工作于亚阈值区的低功耗高线性CMOS混频器

设计了一种采用TSMC 0.13μm CMOS工艺实现的2.4GHz低功耗亚阈值有源混频器,已应用于射频卫星电视接收机中。为了取得较高的线性度,该混频器引入交叉耦合技术以及级间匹配技术,并引入电流注入技术以提高混频器的增益。最终芯片测试结果表明,该混频器在仅消耗1.6mW功耗的状态下,输入三阶交调点IIP3高达5.41dBm,增益高达9.07dB,噪声系数为12.05dB。该混频器的版图尺寸为0.91mm×0.98mm。     

A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 Ω. The opamp provides a maximum output swing of 700 μA, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering.He is currently Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer, 1985) and with the Technical University of Wien, Austria (Summer, 1987).In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

高性能Rail-to-Rail恒定跨导CMOS运算放大器

基于UMC的0.6μm BCD 2P2M工艺,探讨了一种高性能Rail-to-Rail恒定跨导CMOS运算放大器.该运算放大器的输入级采用互补差分对,其尾电流由共模输入信号来控制,以此来保证输入级的总跨导在整个共模范围内保持恒定.输出级采用ClassAB类控制电路,并且将其嵌入到求和电路中,以此减少控制电路电流源引起的噪声和失调.为了优化运算放大器低频增益、频率补偿、功耗及谐波失真,求和电路采用了浮动电流源来偏置.该运算放大器采用米勒补偿实现了18MHz的带宽,低频增益约为110dB,Rail-to-Rail引起的跨导变化约为15%,功耗约为10mW.     

Low-Voltage Continuous-Time Filter Based on a CMOS Transconductor with Enhanced Linearity

The proposed design of a low-voltage continuous time filter is based on a CMOS transconductor with enhanced linearity. The compensation principle is used for the reduction of transconductor non-linear distortions. The discussed transconductor consists of two transconductors connected in parallel. The input transistors of the first transconductor are working in the triode region, while the input transistors of the further one are in the saturation. A fifth-order 1 MHz low-pass Bessel filter is synthesized and simulated using transconductors. The supply voltage is equal to +2.5 V. A tuning system of the filter is also simulated and discussed. A comparison shows that the discussed filter provides a higher linearity (from 4 to 9 dB) than the known circuits with the exception of filters based on the amplifier with degeneration. But it is noted that the last approach is difficult to use for the low-voltage application, because the voltage drop on the degeneration resistors limits the possible decrease of the voltage supply.     

A New CMOS Programmable Balanced Output Transconductor and Application to a Mixed Mode Universal Filter Suitable for VLSI

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing a mixed mode universal filter using six BOTAs and two grounded capacitors is also introduced. The filter's gain can be adjusted simply by varying the amplitude of a transconductance through its control voltage without affecting ₀ and Q of the filter. Also, the Q of the filter can be adjusted by a single transconductor independent of ₀. PSpice simulation results for the BOTA circuit and for the universal filter are also given.     

Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 m CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 A of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

A Low Voltage 14-Bit Self-Calibrated CMOS DAC with Enhanced Dynamic Linearity

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology. Saeed Saeedi was born in Tehran, Iran, in 1979. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran in 2001 and 2003, respectively. Since 2002, he has been working with Iran Microelectronics Research Center, IMRC. He is currently working toward the Ph.D. degree. His research interests include analog and digital integrated circuits for communication systems and high performance data converters. Saeid Mehrmanesh was born in Arak, Iran in 1976. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2002. From 2000, he has been working with Iran Microelectronics Research Center as an analog and mixed-mode and RF-IC design engineer. Since 2004, he has been a Ph.D. student at the University of Tehran. His research interests include analog to digital and digital to analog data converters, low voltage and low power CMOS circuits, telecommunication circuits, high speed serial links and RF circuits. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993.From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.This revised version was published online in May 2005 with corrections to the authors affiliations.     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.     

一种性能优良稳定的微功耗CMOS电压积分器

本文提出了一种电源波动影响弱、低温飘、微功耗（〈1μw）的CMOS电压型积分器电路。它利用自偏置的恒流源电路结构以及MOSFETs的亚阈值特性产生一个nA级的恒流源，通过控制电路实现对电容充放电来获得积分电压。并且对电路结构、器件类型和器件尺寸进行了优化。仿真结果表明，得到了独立于电源电压、低温度系数、微功耗的积分电压。     

一种启动电流为0的CMOS低功耗低成本电流源

根据传统电流源结构,设计了一种启动电流为0的CMOS低功耗电流源。电流源的启动电路仅采用一个耗尽型MOS管,电路正常工作后启动电路会自动关断。仿真结果显示电路正常工作后启动部分消耗的电流基本降为0,整个电路功耗24．9μW。这种结构降低了整个电路的功耗,大大节省了芯片面积。电路基于TSMC0．18μm CMOS工艺,电源电压1．8V,仿真软件为Hspice。     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

A resistorless CMOS bandgap reference with low temperature coefficient and high PSRR

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35?µm CMOS process demonstrate that a temperature coefficient of 10.2?ppm/°C is realised with temperature ranging from ?40°C to 140°C, and a power supply rejection ratio of 58?dB is achieved with a maximum supply current of 27?µA. The active area of the presented BGR is 160?×?140?µm².     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

1.25Gb/s CMOS高灵敏度宽动态范围跨阻放大器

采用0.35μm CMOS工艺设计并实现了一种新的应用于1.25Gb/s光纤通信接收机的高灵敏度、宽动态范围跨阻放大器电路。引入电流注入技术提高输入管跨导、优化噪声性能、提高灵敏度。自带直流反馈实现直流消除功能,同时采用自动增益控制机制,提高动态范围。仿真结果表明,该电路具有82.02dBΩ的跨阻增益、872.7MHz的带宽、23.74kHz的低频截止频率,输入等效噪声电流为4.08pA/Hz(1/2),最大输入光信号为+3dBm(2mA),在3.3V的电源电压下,芯片功耗为43.4mW。