1V电源的CMOS开关电容滤波器

本文设计实现了一种低压的开关电容滤波器,该电路采用上华0.8微米标准CMOS工艺实现.本电路是基于一种新的时钟倍增电路实现的一个双二阶带通滤波器,测试结果表明该带通滤波器可以在1V电源电压下正常工作,测试结果与仿真一致.     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

0.9V2.4GHz CMOS低噪声放大器设计

使用TSMC0.18μm RF CMOS工艺,设计一个低电压折叠式共源共栅结构低噪声放大器(LNA).利用性能系数FoM(Figure of Merit)衡量其整体性能,并通过仿真找到使FoM最大的偏置电压.使用Cadence SpectreRF仿真表明,在0.9V电源下,2.4GHz处的反射系数良好.噪声系数NF仅为...     

Analogue four-quadrant CMOS multiplier with resistors

The letter will present an integrated analogue four-quadrant multiplier with resistors in CMOS technology. This circuit has a large dynamic range over supply voltages and good linearity, with nonlinearity error less than 2% even when the input voltages are greater than half of the supply voltages.     

Integrated MOS four-quadrant analogue multiplier using switched-capacitor technique

A fully integrated four-quadrant analogue multiplier based on switched-capacitor technique for realisation of high-speed and high-density analogue LSIs was developed using a MOS VLSI process. Excellent characteristics such as low total harmonic distortion of ?50 dB for two input signals of 1 Vp-p, large dynamic range of 80 dB and fast operation speed of 2 MHz clock rate were obtained. Application to convolvers and correlators is also demonstrated.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

A CMOS switched-capacitor variable line equalizer

The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.     

一种0.9V低电压低本振功率CMOS有源混频器

设计了一种可工作于0.9 V低电压和-5 dBm本振功率的CMOS有源混频器.通过在MOS管栅极和衬底间引入耦合电容,利用衬底效应加快MOS管的导通和截止,使开关对的开关状态更理想,有效地降低混频器的噪声并提高其线性特性.采用0.18 μm CMOS工艺设计,在2.45 GHz本振信号和2.44 GHz射频信号输入下,实验结果表明该混频器可有效地实现混频且具有较好的性能指标:电压转换增益为12.4 dB,输入三阶截断点为-0.6 dBm,输入1dB压缩点为-3.4 dBm,单边带噪声系数为12 dB.     

CMOS analogue current-steering multiplier

A four-quadrant multiplier circuit for realisation in CMOS is proposed and compromises between characteristics of the design are discussed. The design is optimised for use in the analogue VLSI implementation of neutral networks and the results presented demonstrate that the circuit complies with the requirements of this application.<>     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

Four-quadrant CMOS analogue multiplier

A novel two-signal four-quadrant analogue voltage multiplier has been built in CMOS technology. This multiplier relies on the quadratic current/voltage characteristics of MOS transistors in saturation and combines them with switched-capacitor-type voltage dividers and charge transfer circuits to achieve accurate voltage multiplications with low offsets and large dynamic ranges up to several volts throughout the audio frequency range.     

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.     

High-frequency CMOS switched-capacitor filters for communications application

Bandpass filters for communications applications are realized using an 80 MHz differential single-stage CMOS operational amplifier and a fully differential identical-resonator elliptic bandpass ladder filter configuration. Experimental results are given for a CMOS sixth-order 260 kHz elliptic bandpass filter with a Q-factor of 40, a clock frequency of 4 MHz, and a power dissipation of 70 mW.     

CMOS multiplier for grounded capacitors

A CMOS circuit suited particularly to magnifying the value of a grounded unit capacitor is presented. The multiplication factor is achieved through the gain of current mirrors and its maximum value is limited solely by power consumption constraints. Solutions are then developed to reduce power dissipation, to enable the detection of small unit capacitances, and to enlarge the operating frequency bandwidth     

CMOS/SOS serial-parallel multiplier

A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil/spl times/170 mil chip. The operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand, a, to form the serial product. An addend, b, can also be accommodated to produce ax+b. The design of the multiplier cells are based on functional majority logic adders and weak or trickle inverter master-slave latches. The chip operates at clock rates up to 18 MHz. Power dissipation at 10 MHz and V/SUB DD/ of 5 V is about 20 mW, and the energy consumption for multiplying two 16-bit numbers is about 64 nJ. Typical application areas are mentioned.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Current-mode CMOS quaternary multiplier circuit

A new current-mode CMOS quaternary multiplier circuit is presented. This circuit accepts two 4-valued input currents and a 3-valued CARRY input current and generates a 4-valued SUM output current and a 3-valued CARRY output current. It uses 49 MOS transistors and generates the product in ~10 μs, worst case, in simulations     

New four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.     

A low-power CMOS analog multiplier

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.     

Programmable CMOS switched-capacitor biquad using quasi-passivealgorithmic DAC's

This paper describes an electrically programmable switched-capacitor (SC) biquad using quasi-passive algorithmic digital-to-analog converters (DAC's). Since only two equal-valued capacitors are needed for programming each capacitance value, the proposed technique offers compact, cost-effective programmability when compared to traditional programming techniques employing binary-weighted capacitor-arrays (C-arrays). A demonstration prototype chip realized in a 1.2 μm CMOS double-metal double-poly technology, and which implements an 8 b programmable SC biquad giving a wide range of lowpass, bandpass and highpass filtering functions, occupies an active area of only 0.38 mm²