Software-programmable digital pre-distortion on new generation FPGAs

In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among the hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used Vivado high-level synthesis (HLS) tool as the design tool for the programmable logic. Furthermore, we have compared two different techniques for the integration of hardware and software components, where we have chosen the one with better area/latency trade-off. We present a comprehensive study reporting the DPD parameter update times when exploring the partitioning of the functionality among hardware and software. For low-complexity algorithms, we show that a software-only solution is applicable after carrying out the processor-specific software optimizations. For higher-complexity algorithms, we use Vivado HLS to accelerate the time-consuming blocks in the programmable logic, leading to a speed-up factor of up to 7× in the overall algorithm execution time. We present the performance results for two target devices. We also show that our accelerators use only a small portion of the programmable logic fabric on these devices and that a significant reduction of the system’s energy consumption can be obtained by leveraging the FPGA fabric.     

微机接口芯片地址编码设计的系统化方法

本文给出了微机存储器扩展和I／O接口装置中关于也址编码的一种系统化设计方法。该方法的核心是建立一个各I／O器件和存储器件的地址表，并根据地址空间的分配来设定与每一个器件相关的每一根地址线的逻辑电平。地址表使硬件设计人员清楚明了各硬件的地址安排，给硬件系统的设计带来很大方便。本文还给出了数据线、控制信号线以及地址编码的设计规则，文中所述方法对于分析已设计好的系统也是适用的。     

Failure Analysis of VLSI by IDDQ Testing

A method for enhancing the popular failure techniques has been presented. The method was built on three principles: CMOS devices only draw power during switching operation; fault defects, both floating and stuck will consume power if properly conditioned; bridging fault model test programs combined with the combinational logic designs, the elevated power state should surface at some vector point prior to the location of the falling vector. A system was constructed by making use of an older vintage emission microscope. The system was configured so that direct docking to existing production hardware is possible. Using this system, five case studies were presented. The case studies proved that quiescent current signature scan analysis was successful at locatingthe defects within the failing units after conventional failure analysis techniques had been exhausted. Both bridging faults and floating faults were detected.     

Circuit activity based logic synthesis for low power reliableoperations

A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples     

Unifying simulation and execution in a design environment for FPGAsystems

Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: (1) availability of the hardware during design and debug; (2) programmability; and (3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10000× faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware     

Compaction-based concurrent error detection for digital circuits

We present a non-intrusive concurrent error detection (CED) method for combinational and sequential digital circuits. We analyze the optimal solution model and point out the limitations that prevent logic synthesis from yielding a minimal-cost monolithic CED implementation. We then propose a compaction-based alternative approach for restricted error models. The proposed method alleviates these limitations by decomposing the CED functionality into: compaction of the circuit outputs, prediction of the compacted responses, and comparison. We model the fault-free and erroneous responses as connected vertices in a graph and perform graph coloring in order to derive the compacted responses. The proposed method is first discussed within the context of combinational circuits, with zero detection latency, and subsequently extended to Finite State Machines (FSMs), with a constant detection latency of one clock cycle. Experimental results demonstrate that the proposed method achieves significant hardware reduction over duplication-based CED, while detecting all possible errors.     

Memristor-based combinational circuits: A design methodology for encoders/decoders

The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2ⁿ×n (n×2ⁿ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.     

Future mobile devices — an overview of emerging device trends,and the impact on future converged services

Converged services are attractive for both consumers and operators, as they can offer seamless access across a wide range of networks and devices. In order to support convergence, end-user devices must support a minimum set of hardware and software functionality. The growth of innovation within the hardware and software providers for mobile devices has moved us a step closer to such converged services for common, off-the-shelf devices. This paper describes the underlying trends supporting this, and highlights some key areas of focus for the industry. It also considers a case study of implementing a converged voice service on a current converged device. Finally, future developments are considered, including the contribution that different parts of the industry are making to ensure that users can consume converged services on a wide range of devices.     

The probability of error detection in sequential circuits using random test vectors

In this article a method is presented for evaluating the probability of detecting (PD) a single stuck-fault in a sequential circuit as a function of the number of random input test vectors. A discrete parameter Markov-model is used in the analysis to obtain closed-form expressions for PD. The circuit is partitioned into three parts, the input and output combinational logic and the memory. The analysis is based upon the stationary-state transition matrix associated with a circuit, and the probability that a fault in one of the partitions produces an error at the output of that partition when a random input vector is applied. Results are presented to show how this problem can be reduced to that of testing an equivalent combinational circuit.     

Phase detector for PLL-based high-speed data recovery

A new phase detector for high-speed data recovery is introduced. It uses combinational logic circuits along with signals inherently available in multi-stage voltage-controlled oscillators (VCO) of readily derivable from an arbitrary VCO. The resultant stateless phase detector has a very simple architecture and can operate at higher speeds than is achievable with existing state-based phase detectors.     

TrueFFS文件系统技术研究及实现

TrueFFS技术的出现为丰富的flash存储设备提供了一个统一的块设备接口。论文简要介绍了TrueFFS的工作原理,说明其在flash存储应用中的关键作用,并通过实际案例展示了TrueFFS的硬件实现特点。文中系基于VxWorks操作系统所写,但目前TrueFFS几乎已支持所有的操作系统。     

Synthesis for logical initializability of synchronous finite-statemachines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator. In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finite-state machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesis-for-initializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gate-level circuits are logically initializable. The above two synthesis steps have been incorporated into a computer-aided design tool, SALSIFY, targeted to both two-level and multilevel implementations     

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models     

Open devices — their role in supporting converged services

Converged services are attractive for both consumers and operators, as they can offer seamless access across a wide range of networks and devices. In order to support convergence, end-user devices must support a minimum set of hardware and software functionality. The growth of open operating systems on mobile devices offers the possibility of providing converged services on common, off-the-shelf devices. This paper describes the benefits of such an approach. It also looks at the hardware and software requirements for such a device, and the current level of support for them. Potential pitfalls are discussed, including market fragmentation, software integration and control over the user experience. Finally, future developments are considered, including the evolution of the open operating systems, their push into lower-end devices, and their ability to support next generation networks.     

mMIG: Inversion optimization in majority inverter graph with minority operations

Majority inverter graph is a logic representation structure that along with its algebraic properties synthesizes circuits with improved area, delay, and speed metrics, as compared to conventional And-Invert graph (AIG) realization. In this paper, we propose mMIG synthesis approach, where we aim to minimize the number of inverters in such circuits by adopting minority logic in addition to majority and inversion operations in the logic representation. We propose a set of Boolean transformation methods and derived theorems for minority, majority, and inverter operations. We demonstrate that minority operation in addition to majority and inversion operations significantly optimizes the hardware footprint of combinational circuits and cryptographic primitives, such as linear operations and substitution boxes in several lightweight block ciphers. The area optimization is considered with reduction in count of complemented edges or inversion operations. As results demonstrate, the inversion operations have been reduced from 57.7% to 93.3% in mMIG synthesis approach as compared to MIG logic synthesis in EPFL combinational benchmark suite. In round function implementations of lightweight block ciphers such as SIMON, and ARX boxes such as MARX-2 and SPECKEY, the count of complemented edges in mMIG synthesis technique has been reduced by almost 50% as compared to that in MIG based implementations.     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

Finite state machine synthesis with embedded test function

We propose a synthesis for a testability method in which the test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as an FSM with the same number of state variables as the given object machine. Based upon the chosen test methodology, a variety of test functions can be defined. As an illustration, we construct a test machine in which each state is uniquely set and observed by an input sequence no longer than log _k n, wheren is the number of states and the integerk is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.     

Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes

In this paper, we propose an improvement of the normalized min-sum (MS) decoding algorithm and novel MS decoder architectures with reduced word length using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The proposed normalized MS algorithm introduces a more exact adjustment with two optimized correction factors for check-node-updating computations, while the conventional normalized MS algorithm applies only one correction factor. The proposed algorithm provides a significant performance gain without any additional computation or hardware complexity. The finite word-length analysis in implementing an LDPC decoder is a very important factor since it directly impacts the size of memory to store the intrinsic and extrinsic messages and the overall hardware area in the partially parallel LDPC decoder. The proposed nonuniform quantization scheme can reduce the finite word length while achieving similar performances compared to a conventional quantization scheme. From simulation results, it is shown that the proposed 4-bit nonuniform quantization scheme achieves an acceptable decoding performance, unlike the conventional 4-bit uniform quantization scheme. Finally, the proposed MS decoder architectures by the nonuniform quantization scheme provide significant reductions of 20% and up to 8% for the memory area and combinational logic area, respectively, compared to the conventional 5-bit ones.      

Co-Synthesis to a Hybrid RISC/FPGA Architecture

Hybrid architectures combining conventional processors with configurable logic resources enable efficient coordination of control with datapath computation. With integration of the two components on a single device, housekeeping tasks and, optionally, loop control and data-dependent branching, can be handled by the conventional processor, while regular datapath computation occurs on the configurable hardware. This paper describes a novel approach to programming such hybrid devices that gives the programmer control over mapping of data and computation between conventional processor and configurable logic. With a simple set of pragma and intrinsic function directives, the NAPA C language provides for manual control over perhaps the most important aspect of programming such hybrid devices. Alternatively, as experience is gained about tradeoffs between the two computational resources, mapping directives may eventually be generated by an external tool. The paper further describes a research prototype compiler that targets the hybrid processor model, with a concrete implementation for the National Semiconductor NAPA1000 chip. The NAPA C compiler parses the mapping directives, performs semantic analysis, and co-synthesizes a conventional processor executable combined with a configuration bit stream for the configurable logic. Two major compiler phases, the synthesis of pipelined loops and the datapath synthesis, are described in detail.