Cryptographically-enforced hierarchical access control with multiple keys

Hierarchical access control policies, in which users and objects are associated with nodes in a hierarchy, can be enforced using cryptographic mechanisms. Protected data is encrypted and authorized users are given the appropriate keys. Lazy re-encryption techniques and temporal hierarchical access control policies require that multiple keys may be associated with a node in the hierarchy. In this paper, we introduce the notion of a multi-key assignment scheme to address this requirement. We define bounded, unbounded, synchronous, and asynchronous schemes. We demonstrate that bounded, synchronous schemes provide an alternative to temporal key assignment schemes in the literature, and that unbounded asynchronous schemes provide the desired support for lazy re-encryption.     

Networked iterative learning control design for discrete-time systems with stochastic communication delay in input and output channels

This paper develops two kinds of derivative-type networked iterative learning control (NILC) schemes for repetitive discrete-time systems with stochastic communication delay occurred in input and output channels and modelled as 0-1 Bernoulli-type stochastic variable. In the two schemes, the delayed signal of the current control input is replaced by the synchronous input utilised at the previous iteration, whilst for the delayed signal of the system output the one scheme substitutes it by the synchronous predetermined desired trajectory and the other takes it by the synchronous output at the previous operation, respectively. In virtue of the mathematical expectation, the tracking performance is analysed which exhibits that for both the linear time-invariant and nonlinear affine systems the two kinds of NILCs are convergent under the assumptions that the probabilities of communication delays are adequately constrained and the product of the input–output coupling matrices is full-column rank. Last, two illustrative examples are presented to demonstrate the effectiveness and validity of the proposed NILC schemes.     

Efficient Implementation of Synchronous Communication over Asynchronous Networks

The implementation of synchronous communication primitives over asynchronous message-passing networks is investigated. Efficient algorithms are presented for the committee coordination problem and its more dynamic version called the first-order interaction problem. A new notion of strong fairness called 1-sf and algorithms achieving it are also described. It is further shown that any stronger notion of fairness cannot be implemented.     

量子密钥分配的通信模型研究

本文通过引入量子测量信道的概念，并参照经典通信模型，首次为量子密钥分配建立了通信模型。量子密码中已提出的量子密钥分配协议可以统一地用本文提出的模型描述，模型的建立有利于量子密码的进一步研究和在通信网络中的应用。     

Algorithms for scheduling with applications to parallel computing

Scheduling of message passing for synchronous communication is found to be equivalent to colouring the edges of a graph without conflict. The graph edge-colouring problem, which has other applications, is studied. An algorithm which colours the graph with no more than deg + 1 colours, where deg is the degree of the graph, is implemented. The problem of minimising the sum of the largest weight for each colour is also investigated and an algorithm suggested. These algorithms are used to organise the communication as part of a finite element Euler solver. Different communication schemes and their effect on the performance of the flow solver are compared.     

An Input/Output Semantics for Distributed Program Equivalence Reasoning

A new notion of input/output equivalence of distributed imperative programs, with synchronous communications, is introduced. It preserves the input/output relation, encompassing both, initial/final state and communication channel values. For its mathematical justification, the semantic framework of Manna and Pnueli, based on finite transition systems and reduced behaviors, is extended with the notion of input/output behavior. A set of laws for the equivalence is overviewed. A deduction rule for the substitution of references to input/output equivalent procedures is defined and justified in the new semantics. The rule is applied to decompose distributed program simplification proofs, introduced in a prior work, which use the laws to establish the equivalence between a sequential and a parallel communicating program. They include communication elimination as one of their steps. An outline of one of such proofs, for a pipelined processor model, is included.     

Intel 8098／8051单片机的多机互连方案的研究

本文讨论了多单片机的几种互连方案，并针对８０９８／８０５１，利用本身的资源，设计了公共总线方案，对该方案的循环判优逻辑，同步机制，通信邮箱分配和时间指标等进行了详细的分析，为实际应用奠定了基础。     

Reactive Modules

We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee) and hierarchical (stepwise-refinement) design and verification. While synchronous models are based on a notion of atomic computation step, and asynchronous models remove that notion by introducing stuttering, our model is based on a flexible notion of what constitutes a computation step: by applying an abstraction operator to a system, arbitrarily many consecutive steps can be collapsed into a single step. The abstraction operator, which may turn an asynchronous system into a synchronous one, allows us to describe systems at various levels of temporal detail. For describing systems at various levels of spatial detail, we use a hiding operator that may turn a synchronous system into an asynchronous one. We illustrate the model with diverse examples from synchronous circuits, asynchronous shared-memory programs, and synchronous message-passing protocols.     

A Survey and Taxonomy of GALS Design Styles

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.     

Trace and Testing Equivalence on Asynchronous Processes

We study trace and may-testing equivalences in the asynchronous versions of CCS and π-calculus. We start from the operational definition of the may-testing preorder and provide finitary and fully abstract trace-based characterizations for it, along with a complete in-equational proof system. We also touch upon two variants of this theory by first considering a more demanding equivalence notion (must-testing) and then a richer version of asynchronous CCS. The results throw light on the difference between synchronous and asynchronous communication and on the weaker testing power of asynchronous observations.     

Distributed edge event‐triggered consensus protocol of multi‐agent systems with communication buffer

This paper proposes a distributed edge event‐triggered (DEET) scheme of multi‐agent systems via a communication buffer to reduce unnecessary update of controllers induced by fast information transmission. This edge scheme avoids a synchronous phenomenon in node event‐triggered mechanism, in which the triggering of one agent activates information transmission of all edges linked with this agent. Hence, the node event‐triggered scheme leads to unnecessary update of control protocols while the DEET provides a new approach without constrains on synchronous phenomenon of edge information exchange. That is, the communication on each edge is independent with other edges. In addition, we investigate another case where edge information transmission is subject to quantization and a quantized edge event‐triggered control protocol is proposed. Note that such a quantized protocol guarantees asymptotical consensus instead of bounded consensus in most of the existing literature. Meanwhile, both DEET and quantized edge event‐triggered schemes have nontrivial properties of excluding Zeno behavior. Furthermore, an algorithm is provided to avoid continuous event detection; hence, the communication traffic of the whole network is reduced significantly. Copyright © 2016 John Wiley & Sons, Ltd.     

A dynamic analysis of the interplay between asynchronous and synchronous communication in online learning: The impact of motivation

With the increased affordances of synchronous communication tools, more opportunities for online learning to resemble face‐to‐face settings have recently become available. However, synchronous communication does not afford as much time for reflection as asynchronous communication. Therefore, a combination of synchronous and asynchronous communication in e‐learning would seem desirable to optimally support learner engagement and the quality of student learning. It is still an open question though, how to best design online learning with a blend of synchronous and asynchronous communication opportunities over time. Few studies have investigated the relationship between learners' actual use of synchronous and asynchronous communication over time. Therefore, this study addressed that relationship in an online course (N = 110), taking into account student motivation, and employing a dynamic inter‐temporal perspective. In line with our assumptions, we found some support for the expected association between autonomous motivation and engagement in asynchronous and synchronous communication, be it restricted primarily to the first course period. Also, positive relations between engagement in synchronous and asynchronous communication were found, with the strongest influence from using asynchronous to synchronous communication. This study adds to the knowledge base needed to develop guidelines on how synchronous communication can be combined with asynchronous learning.     

Integrity analysis of authenticated encryption based on stream ciphers

We study the security of authenticated encryption based on a stream cipher and a universal hash function. We consider ChaCha20-Poly1305 and generic constructions proposed by Sarkar, where the generic constructions include 14 AEAD (authenticated encryption with associated data) schemes and 3 DAEAD (deterministic AEAD) schemes. In this paper, we analyze the integrity of these schemes both in the standard INT-CTXT (integrity of ciphertext) notion and in the RUP (releasing unverified plaintext) setting called INT-RUP notion. We present INT-CTXT attacks against 3 out of the 14 AEAD schemes and 1 out of the 3 DAEAD schemes. We then show INT-RUP attacks against 1 out of the 14 AEAD schemes and the 2 remaining DAEAD schemes. Next, we consider ChaCha20-Poly1305 and show that it is provably secure in the INT-RUP notion. Finally, we show that the remaining 10 AEAD schemes are provably secure in the INT-RUP notion.     

Combining synchronous and asynchronous timing schemes for high-performance systems

Globally asynchronous, locally synchronous (GALS) design is emerging as the architecture of choice for certain applications. In a GALS system, the circuitry in each timing domain is locally synchronized, and different clock domains are glued together according to asynchronous communication schemes. This issue of IEEE Design & Test introduces some basic design and validation issues of the GALS architecture. The editorial from the guest editors outlines the scope of this special theme. In addition to the special theme, this issue also includes a special section highlighting the International Test Conference (ITC). Finally, there is a short report of highlights from the 2007 Design Automation Conference held earlier this year.     

An implementation framework for HPF distributed arrays onmessage-passing parallel computer systems

Data parallel languages, like High Performance Fortran (HPF), support the notion of distributed arrays. However, the implementation of such distributed array structures and their access on message passing computers is not straightforward. This holds especially for distributed arrays that are aligned to each other and given a block-cyclic distribution. In this paper, an implementation framework is presented for HPF distributed arrays on message passing computers. Methods are presented for efficient (in space and time) local index enumeration, local storage, and communication. Techniques for local set enumeration provide the basis for constructing local iteration sets and communication sets. It is shown that both local set enumeration and local storage schemes can be derived from the same equation. Local set enumeration and local storage schemes are shown to be orthogonal, i.e., they can be freely combined. Moreover, for linear access sequences generated by our enumeration methods, the local address calculations can be moved out of the enumeration loop, yielding efficient local memory address generation. The local set enumeration methods are implemented by using a relatively simple general transformation rule for absorbing ownership tests. This transformation rule can be repeatedly applied to absorb multiple ownership tests. Performance figures are presented for local iteration overhead, a simple communication pattern, and storage efficiency     

The potential of synchronous communication to enhance participation in online discussions: A case study of two e-learning courses

Computer-mediated communication (CMC) has been adopted in most e-learning settings. However, few research studies have considered the effect of different CMC. This study examined how and why synchronous communication affected participation in online discussions. Two online classes that participated in two asynchronous and two synchronous online discussions were examined. Actual and perceived measures of participation indicated that synchronous communication induced personal participation, which could be regarded as a complement to cognitive participation. Personal participation involves more intense interaction better supported by synchronous communication while cognitive participation is a more reflective type of participation supported by asynchronous communication. In synchronous discussions, the e-learners felt that they worked together and were not restricted to only discuss course content. This was likely to induce arousal and motivation and increased convergence on meaning, especially in small groups.     

TMS320F28xx异步串口通信的研究

针对TI公司的TMS320F28xx,在介绍DSP芯片主要特点的基础上重点阐述了它的串行通信模块,并描述了串行通信模块的两大加强特性,介绍了利用F2812串行通信模块实现其内部CPU与异步外设之间的串行通信的原理,并且结合实际应用,给出了异步串行通信的软件程序设计。实际应用结果表明,该方法数据传输可靠,解决了通信过程中对终端波特率的确定问题．减少了通信中断次数,提高了通信速率,有广泛的应用前景。     

单片机以太网通信实现软硬件操作同步

阐述了软硬件操作同步的基本概念和应用背景,分析了两款用于实现单片机以太网通信的网卡芯片,论证了软硬件操作同步通信协议的选择,以ENC28J60网卡芯片为例,设计了基于单片机以太网通信的软硬件操作同步方案,并给出了实现该方案的关键程序代码。     

Predicting the performance of synchronous discrete event simulation

We develop a model to predict the performance of synchronous discrete event simulation. Our model considers the two most important factors for the performance of synchronous simulation: load balancing and communication. The effect of load balancing in a synchronous simulation is computed using probability distribution models. We derive a formula that computes the cost of synchronous simulation by combining a communication model called LogGP and computation granularity. Even though the formula is simple, it is effective in capturing the most important factors for the synchronous simulation. The formula helps us to predict the maximum speed up achievable by synchronous simulation. In order to examine the prediction model, we have simulated several large ISCAS logic circuits and a simple PCS network simulation on an SGI Origin 2000 and Terascale Computing System (TCS) at the Pittsburgh Supercomputing Center. The results of the experiment show that our performance model accurately predicts the performance of synchronous simulation. The performance model developed is used to analyze the effect of several factors that may improve the performance of synchronous simulation. The factors include problem size, load balancing, granularity, communication overhead, and partitioning.     

基于FPGA的三线制同步串行通信控制器设计

为了简化应用系统中的三线制同步串行通信扩展接口,减小系统体积,降低系统功耗,通过研究三线制同步串行通信的原理,利用FPGA,结合硬件描述语言VHDL,设计了三线制同步串行通信控制器功能框架结构,介绍了各组成模块的功能及工作过程,并对该控制器IP核的接口信号进行了详细描述与定义,最后在Xilinx ISE和ModelSim SE平台下对该控制器IP核进行了综合和功能仿真。