Solder joint reliability of a polymer reinforced wafer level package

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP^® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill.A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps.This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

Trends of power semiconductor wafer level packaging

A review of recent advances in power wafer level electronic packaging is presented based on the development of power device integration. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with next generation wafer level power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.     

晶圆级封装的优化散热分析

通过有限元分析软件ANSYS,对一款晶圆级封装的产品进行有限元分析仿真,讨论了空气对流系数、环境温度、基板厚度、焊球间距等因素对芯片热阻的影响。结果表明:考虑成本、散热等综合因素,选择空气对流系数为25×10–6W/(mm·℃)基板厚度为0.10 mm、焊球间距为0.5 mm为最优参数,可满足实际生产需要。     

Moldless encapsulation for LED wafer level packaging using integrated DRIE trenches

This paper demonstrates a LED wafer level packaging process which employs the glob-top dispensing technique for encapsulation. The process utilizes the constraint effect introduced by the trenches to limit the spreading of encapsulant. This enables the geometry control of encapsulation. Several design and process parameters have been investigated. The study has considered the effect of the trench patterns. A 4-in. silicon wafer is fabricated with a pattern etched by the DRIE process. It serves as a substrate for an LED array employed in the present study. Using the wafer substrate and the glop-top dispensing technique, wafer level LED packaging incorporated with a moldless encapsulation process is realized.     

Anand model and FEM analysis of SnAgCuZn lead-free solder joints in wafer level chip scale packaging devices

In this paper, the constitutive response of SnAgCuZn solder was studied under uniaxial tension. Anand model was used to represent the inelastic deformation behavior of the lead-free solders. The material parameters of the constitutive relations for SnAgCuZn solders were determined from separated constitutive relations and experimental results. In addition, the constitutive model was used to analyze the thermally induced inelastic deformation of the solder joints in wafer-level chip scale packages mounted on printed circuit boards based on finite element analysis. And it is found that the addition of Zn can enhance the fatigue life of SnAgCu solder joint.     

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Accompanying the popularization of portable and handheld products, high reliability under board level drop test is a great concern to semiconductor manufacturers. In this study, a stress-buffer-enhanced package with fan-out capability is proposed to meet the high requirement of drop test performance. Both drop test experiment and numerical simulation were performed. The results showed the first failure of proposed package passed over 100 drops (mean-life-to-failure over 240 drops). Moreover, the failure of broken trace metal in the stress-buffer-enhanced package which is different from the solder joint failure in the conventional wafer level package was observed both in experiments and dynamic simulations. Simulation results were validated with experimental data and explained how the proposed stress-buffer-enhanced package improved drop test performance.     

Impact of substrate resistance and layout on passivation etch-induced wafer arcing and reliability

Wafer arcing, as a form of plasma-induced damage, occurs randomly, varies among different products and introduces problems into production yield and reliability. Conventional arcing theory is based on substrate conductive paths, for which the arcing frequency decreases as the substrate resistance increases. However, we observed the reverse result, i.e., silicon-on-insulator (SOI) and integrated passive device (IPD) wafers with high substrate resistance suffered a high frequency of passivation (PA) etch-induced arcing. In addition, the newly developed through silicon vias (TSV) interposer process for three-dimensional (3D) packaging also encountered a similar problem. To explain and solve these problems, we used substrates of different resistivities using the arcing-enhanced method to study this PA etch-induced wafer arcing phenomenon and revealed the mechanism underlying the effect of substrate resistance, the role of the seal ring, the root cause of the layout’s effect on arcing frequency and the impact on reliability. Next, we determined that the reduction in arcing relies on the simultaneous optimization of the process and the layout and observed that the reduction of the arcing source helps to improve product reliability. Finally, improvement methods and guidelines were proposed for both the process and the layout.     

Optimizing protocol interaction using response surface methodology

Abstract-Response surface methodology (RSM) is a collection of statistical design and numerical optimization techniques traditionally used to optimize industrial processes. In this paper, we demonstrate that the methodology can be successfully applied to the domain of networking. Specifically, we obtain increased throughput with a significant decrease in delay in a ns-2 simulation model of a mobile ad hoc network (MANET) by using RSM to optimize protocol interaction found by factor screening. Whether the experimentation is with a stochastic simulation model or a physical system, such as a MANET or a wireless sensor network test-bed, RSM provides a general and practical methodology to screen factors and robustly and jointly optimize responses.     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations

The main investigation presented in this work is focused on the design and fabrication of redistribution in wafer level chip scale package (RDL in WLCSP) for high power device application. The design considers higher carrier loading incorporated with the dimensional broadening in both lateral and thickness direction of the metal redistribution layer. The lateral broadening shortens the channels of electrical isolation, while the thickness broadening evolves the conventional sputtering into the present electro-plating achieved Cu metallization layer. The innovation brings about the challenge for high power RDL in WLCSP. In this study, the interplay between structural design, process interactions, and possible solutions for high power RDL in WLCSP are presented. To address the arguments, two designs of experiment are conducted. We demonstrate the determinative influence factors, resultant from process interactions, toward the adhesive properties beyond the conventional wisdom.     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

Finite element modeling on electromigration of solder joints in wafer level packages

This work studies the electromigration of solder joints in an encapsulated copper post wafer level package (WLP) by finite element modeling. Experimental data showed that the electromigration failure occurs in solder joints on the printed circuit board (PCB) side due to the current crowding. In order to improve the electromigration performance on the PCB side with a copper post WLP, two new line-to-bump geometry designs are proposed. Coupled electro-thermal finite element modeling is performed to obtain the electrical and thermal fields simultaneously. The ionic flux from electron wind and thermal response is calculated based on finite element solutions. The divergence of the total flux, which is the sum of the divergence of electromigration and thermomigration, is extracted at the critical locations in solder joints. Results show that the new proposed design structures can reduce the maximum current density by 19%, and the divergence of the total ionic flux by 42%. Thermal gradient is very small in solder joints, therefore, the main driving force for electromigration failures comes from the electron wind. The finite element results on mesh dependency are discussed in this paper.     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Solder joints inspection using a neural network and fuzzyrule-based classification method

In this paper, we described an approach in automation, the visual inspection of solder joint defects of surface mounted components on a printed circuit board, using a neural network with fuzzy rule-based classification method. Inherently, the solder joints have a curved, tiny, and specular reflective surface. This presents the difficulty in taking good images of the solder joints. Furthermore, the shapes of the solder joints tend to greatly vary with their soldering conditions, and are not identical with each other, even though some of the solder joints belong to a set of the same soldering quality. This problem makes it difficult to classify the solder joints according to their properties. To solve this intricate problem, a new classification method is here proposed which consists of two modules: one based upon an unsupervised neural network, and the other based upon a fuzzy set theory. The novel idea of this approach is that a fuzzy rule table reflecting the knowledge of criteria of a human inspector, is utilized in order to correct any possible misclassification made by the neural network module. The performance of the proposed approach was tested on numerous samples of printed circuit boards in commercially available computers, and then compared with that of a human inspector. Experimental results reveal that the proposed method is superior to the neural network classification method alone, in terms of its accuracy of classification     

An evaluation of fast wafer level test methods for interconnect reliability control

A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times.     

Congestion avoidance in cognitive wireless sensor networks using TOPSIS and response surface methodology

Congestion in wireless sensor networks degrades the quality of the channel and network throughput. This leads to packet loss and energy dissipation. To cope with this problem, a two-stage cognitive network congestion control approach is presented in this paper. In the first stage of the proposed strategy, initially downstream nodes calculate their buffer occupancy ratio and estimate congestion degree in the MAC layer. Then, they send the estimated value to both network and transport layers of their upstream nodes. The network layer of the upstream node uses TOPSIS in order to rank all neighbors to select the best one as the next relay node. In the second stage, transport layer of the given node adjusts the transmission rate using an optimized regression analysis by RSM. Extensive simulations demonstrated that the proposed method not only decreases packet loss, but also significantly improves throughput and energy efficiency under different traffic conditions, especially in heavy traffic areas. Also, Tukey test is used to compare performance of algorithms as well as to demonstrate that the proposed method is significantly better than other methods.     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

A new wafer level reliability method for evaluation of ionic induced pmosfet drift effects

An ionic induced pMOSFET drift effect was investigated by deliberately enhancing the sodium concentration in interlevel dielectric layers.High frequency capacitance voltage and triangular voltage sweep (TVS) measurements as well as different bias temperature stress sequences were employed to show that the degradation is a two step process: sodium drift into active areas and charging of traps which were generated by sodium interactions with the semiconductor oxide interface.A special wafer level reliability method was developed which takes into consideration the two phase nature of the failure mechanism.