Fully ion-implanted InP JFET with buried p-layer

Implementation of a buried p-layer in a fully ion implanted InP JFET is discussed. Using Be coimplanted with Si, a sharp channel profile is obtained. The saturation current has been reduced, and the pinch-off characteristic has been improved, with a slight decrease in transconductance and cutoff frequency. The equivalent circuits for the JFET with and without the buried p-layer are compared     

Enhanced high-frequency performance in a GaAs, self-aligned, n-JFETusing a carbon buried p-implant

C ion implantation has been employed, for the first time, to form the buried p-layer in GaAs, self-aligned, ion implanted JFETs. Comparable DC performance was seen for JFETs with C or Mg implants; however, C-backside JFETs showed superior high-frequency performance. High dose C-backside devices had a f_t of 28.3 GHz and a f_max of 43.2 GHz for a 0.5 μm gate length that were 28% and 46% higher, respectively, than comparable Mg-implanted JFETs. This enhancement is a result of the lower C_gs in the C-backside device resulting from he inherently low activation of the implanted C below the channel while the C still effectively compensated the tail of the Si-channel implant. This approach relaxes the trade-off between optimizing the DC and the AC performance for the buried p-implant in GaAs JFETs and MESFET's     

退火工艺对Al离子注入的4H-SiC表面形貌的影响

通过应用多次Al离子注入和CVD中的高温退火技术,在SiC片表面形成了p型层。p型层中各深度下Al的浓度均为110¹⁹cm^-3,层厚为550nm。本文应用三种不同的退火工艺对注入后的SiC进行退火。通过测量和比较表面粗糙度,发现通过石墨层覆盖来保护表面的退火工艺可以很好的阻止SiC表面在高温退火下的粗化,粗糙度保持在3.8nm。通过其他两种(在氩气保护下、在SiC保护片的覆盖下)退火工艺退火所得到的表面有明显的台阶,粗糙度分别为12.2nm和6.6nm。     

Effect of p-doped overlayer thickness on RF-dispersion in GaNjunction FETs

Successive reactive ion etchings (RIE) were performed on the access regions of p⁺-n GaN JFETs. A decrease in the n-layer sheet resistance, with a consequent increase in I_DSS was detected after complete removal of the p-layer, due to a reduction in the n-layer depletion region. An increase in RF-dispersion was experienced, as a result of the progressive reduction of screening from surface-states originally provided by the overlying p-cap layer. No dispersion was detected before cap removal. A continuous increase in f _t and f_max was detected even before complete removal of the p-layer, due to virtual gate length reduction. It is expected that an optimized p-doped overlayer will provide current slump suppression without degradation in cutoff frequency or breakdown     

A novel double RESURF LDMOS for HVIC's

The viability of a fully implanted double RESURF technology using a linearly varying doping of p-layer at the surface [Electron. Lett. 32 (12) (1996) 1092-1093] is demonstrated for the first time. Incorporating such a layer allows the drift region charge to be doubled without degradation of breakdown voltage. Experimental results of a high-voltage LDMOS in such a technology show a reduction in the on-resistance by one-half of that of a conventional RESURF based structure.     

A lightly doped deep drain GaAs MESFET structure for linearamplifiers of personal handy-phone systems

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 Ω/mm for the BP-LD3 structure indicate high potentiality for analog applications     

甲烷流量对8.5代非晶硅光伏组件P层材料结构和光学性质的影响

本文研究了甲烷流量对作为工业非晶硅光伏组件的p层材料—非晶碳化硅结构和光学性质的影响.p层非晶碳化硅薄膜采用硅烷和甲烷混合气体在射频等离子体增强化学气相沉积(RF-PECVD)设备中沉积制得,该设备是应用材料公司制造的尺寸为2.2 m × 2.6 m的8.5代系统.采用红外光谱和透射/反射谱分析与沉积工艺相关的键结构和光学性质.相同工艺条件下,当甲烷含量从3000 sccm增加到8850 sccm, p层非晶碳化硅薄膜的光学带隙逐步增加. p层非晶碳化硅薄膜的沉积速率随甲烷流量的增加而逐渐减小,其原因是硅烷-甲烷等离子体中SiH3粒子的减少.文中还通过在不同位置取样和分析沉积速率研究了大面积薄膜的均匀性.     

亚微米GaAs MESFET二维数值模拟

本文用计入热电子效应的动量能量守恒模型讨论了亚微米GaAs MESFET二维数值模拟。为了减少计算量进行了模型简化和算法选择。文中给出并分析了三种典型器件的模用范果,根据模拟结果,研究了小尺寸器件中的速度过冲效应并得出常规的漂移扩散模型的适拟结围。     

Alpha-particle-induced charge collection in p-n junction diodes insemi-insulating GaAs substrates

The bias and angle dependences of the alpha-particle-induced charge collected by GaAs p-n junction diodes are investigated. These diodes, in which the n-layer overlays the p-layer, are fabricated in a semi-insulating GaAs substrate by Si and Mg ion implantation. ²⁴¹ Am placed in a vacuum is used as an alpha-particle source with an initial energy of 4.03 MeV and a fluence of 5.4×10^-5/s/μm². The results show that the collected charge is nearly independent of the applied bias. This bias independence may be further evidence that the charge funneling process is not important in semi-insulating GaAs. A model not incorporating funneling can explain the measured angular dependence. Based on this model, the design principle for the buried p-layer structure is discussed     

Improvement of alpha-particle-induced soft-error immunity in a GaAsSRAM by a buried p-layer

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10⁴ at an alpha-particle fluence of about 2.0×10⁴ cm^-2-s^-1 with a 1.0-μCi²⁴¹Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs     

An integrated 500-V power DMOSFET/antiparallel rectifier devicewith improved diode reverse recovery characteristics

We propose and demonstrate an integrated power MOSFET structure where a fast-switching antiparallel rectifier with improved reverse recovery is integrated within the conventional DMOSFET structure. In this device, the source metal electrode of the DMOSFET is extended to the n-drift region, and a thin p-layer is implanted under the metal forming a junction diode antiparallel to the DMOSFET. Analysis of the experimental switching performance of the integral diode in 500-V integrated power DMOSFET/antiparallel rectifier devices indicates at least 30% decrease in peak reverse current and minority carrier stored charge at 100°C     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

A self-aligned gate GaAs MESFET with p-pocket layers forhigh-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz π/4-shift QPSK modulated input     

Below 10 ps/gate operation with buried p-layer SAINT FETs

GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance.     

Effects of a buried p-layer on alpha-particle immunity of MESFET's fabricated on semi-insulating GaAs substrates

Measurements of alpha-particle-induced charge are carried out for the first time on both conventional MESFET's fabricated directly on semi-insulating GaAs substrates and MESFET's with a buried p-layer. The maximum collected charge is found to be 65 fC in the MESFET's with a buried p-layer, one order smaller than in conventional MESFET's.     

Influence of growth temperature and growth rate of p-GaN layers on the characteristics of green light emitting diodes

We investigated the electrical and structural qualities of Mg-doped p-type GaN layers grown under different growth conditions by metalorganic chemical vapor deposition (MOCVD). Lower 300 K free-hole concentrations and rough surfaces were observed by reducing the growth temperature from 1,040°C to 930°C. The hole concentration, mobility, and electrical resistivity were improved slightly for Mg-doped GaN layers grown at 930°C with a lower growth rate, and also an improved surface morphology was observed. In_0.25Ga_0.75N/GaN multiple-quantum-well light emitting diodes (LEDs) with p-GaN layers grown under different conditions were also studied. It was found from photoluminescence studies that the optical and structural properties of the multiple quantum wells in the LED structure were improved by reducing the growth temperature of the p-layer due to a reduced detrimental thermal annealing effect of the active region during the GaN:Mg p-layer growth. No significant difference in the photoluminescence intensity depending on the growth time of the p-GaN layer was observed. However, it was also found that the electroluminescence (EL) intensity was higher for LEDs having p-GaN layers with a lower growth rate. Further improvement of the p-GaN layer crystalline and structural quality may be required for the optimization of the EL properties of long-wavelength (∼540 nm) green LEDs.     

脉冲钨离子注入4Cr5MoV1Si钢改善其耐磨性的研究

采用由金属蒸汽真空弧（MEVVA）离子源引的强束流脉冲金属钨离子对4Cr5MoV1Si(H13)钢进行了离子注入表面改性研究,用针盘式磨损机测得样品的耐磨性提高两部左右,使用卢瑟福背散射谱（RBS）测量了钨在样品中的浓度深度分布,采用X射线衍射考察了注入样品的表面微结构,按照非线性碰撞理论,讨论了样品的耐磨性,表面成分,结构与注入参数（主要是注入能量和注入束流密度）的关系。     

用p埋层CMOS工艺制造横向磁敏晶体管

本文介绍了一种用P埋层CMOS工艺制造的横向磁敏晶体管(LMT)。器件结构是双基极、双集电极npn晶体管。它具有抑制侧向注入效应,即将注入集中于发射区的中部,在中性基区的少数载流子受到双重偏转作用,消除了横向无功电流。在CMOS工艺的基础上加了P埋层,消除了纵向无功电流。器件对磁场有良好的线性响应。     

p-Layer bandgap engineering for high efficiency thin film silicon solar cells

Spectroscopic ellipsometry (SE), high resolution transmission electron microscopy (HRTEM), atomic force microscopy (AFM) and optical transmittance measurements were used to study and establish a correlation between the open-circuit voltage (V_oc) of solar cells and the p-layer optical band gap (E_p). It is found that the ellipsometry measurement can be used as an inline non-destructive diagnostic tool for p-layer deposition in commercial operation. The analysis of ellipsometric spectra, together with the optical transmittance data, shows that the best p-layer appears to be very fine nanocrystallites with an E_p 1.95 eV. HRTEM measurements reveal that the best p-layer is composed of nanocrystallites ~9 nm in size. It is also found that the p-layer exhibits very good transmittance, as high as ~91.6% at ~650 nm. These results have guided us to achieve high V_oc value 1.03 V for thin film silicon based single junction solar cell.     

Quasi-direct UV/blue GaP avalanche photodetectors

GaP avalanche photodiodes, with thin device layers have been processed, utilizing both p-i-n and recessed window p-i-n structures, as well as a Schottky structure. The results showed low dark currents, good quantum efficiency (QE), and high gains up to 10/sup 3/, with good uniformity across the wafer. The peak QE at 440 nm indicated /spl Gamma/-valley absorption, rather than band-edge absorption. The recess window photodiodes exhibited enhanced UV detection as a result of reduced absorption and recombination in the undepleted p-layer. Additionally, the Schottky structure demonstrated potential for further enhanced UV detection, by employing a thin semitransparent contact.