Hot carrier effects on analog performance of N- and P-MOSFET's withoxynitride gate dielectrics

In this paper we report the impact of hot-carrier stress on analog performance of n- and p-MOSFET's with conventional oxide, NH₃-nitrided oxide (RTN) and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics. Changes due to hot-carrier stress in crucial analog parameters viz., drain output resistance, voltage gain, and input offset voltage of a source coupled differential MOSFET pair are investigated. Results show that RTN/RTO gate dielectrics suppress degradation of analog parameters in n-MOSFET's but increase it slightly in p-MOSFET's, as compared to conventional oxide MOSFET's     

Precise modeling of hot carrier gate current in short-channelMOSFET's

A powerful model which considers the fact that the values of the channel and carrier temperatures T and T_c vary with position in the bulk and channel is considered. It reveals that the energy distribution of hot carriers deviates from the well-known Maxwellian distribution by a small but nonnegligible perturbation and evaluates the dependence of this deviation of the device technology, geometry, and biasing conditions. The model helps to remove important discrepancies between the old hot-carrier models and measurements     

Direct evidence of gate oxide thickness increase in tungstenpolycide processes

The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide were analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are ~244 and ~285 Å for as-deposited and 1000°C annealed samples, respectively. The TEM results agree with those from CV measurements. The TEM analyses provide direct physical evidence of an additional oxide thickness (~41 Å) during the W-polycide annealing     

Temperature dependence of hot carrier effects in short-channelSi-MOSFETs

Full-band Monte Carlo simulations were carried out to investigate hot carrier effects associated with impact ionization under the lateral electric field profiles typical of submicrometer Si-MOSFETs. It is shown that the temperature dependence of the band-gap energy of Si plays an important role for hot carrier suppression at low temperature in submicrometer devices. On the other hand, as the device size shrinks into the sub-0.1 regime, in which the high-field region is comparable in size to or smaller than the energy relaxation length, the number of electrons with energy below the supply drain voltage becomes less sensitive to temperature. As a result, the suppression of impact ionization at low temperature in sub-0.1 μm devices could be ascribed to both quasi-ballistic transport characteristics and temperature-dependent band-gap energy     

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.     

Effects of AC hot carrier stress on n- and p-MOSFET's withoxynitride gate dielectrics

Effects of AC hot carrier stress on n- and p-MOSFET's with pure, NH₃-nitrided (RTN) and reoxidized nitrided (RTN/RTO) gate oxides are studied. Irrespective of the gate dielectric used, n-MOSFET's show enhanced degradation but p-MOSFET's show suppressed degradation under AC stress as compared to DC stress for the same duration. Dependence of degradation on frequency and duty cycle of gate pulse is studied. Results show that the degradation under AC stress in n-MOSFET's is suppressed whereas it is increased slightly in p-MOSFET's with the use of RTN/RTO gate oxides instead of conventional gate oxides     

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF₂ implanted p⁺ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 Å regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon     

Improvement in hot carrier lifetime as a function of N2ion implantation before gate oxide growth in deep submicron NMOS devices

A detailed study of the impact of N₂ ion implantation (I/I) dose before gate oxide growth to hot carrier (HC) reliability of NMOSFETs is reported here, Improvements of more than 20× in HC lifetime were achieved by the introduction of sufficiently high N₂ (I/I) doses. It was found that for NMOSFETs, the HC degradation correlates inversely to the initial interface state density introduced by the N₂ I/I process. This process-driven HC lifetime improvement does not require extensive post-metal anneals for HC lifetime improvements in advanced CMOS multilevel metal-dielectric processes     

Improved method for the oxide thickness extraction in MOSstructures with ultrathin gate dielectrics

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique and of Vincent's method is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm to 1.8 nm     

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

The progressive wear-out of a breakdown path in ultra-thin gate oxides depends on oxide thickness and follows the intrinsic voltage acceleration model of time to breakdown. The quantification of progressive wear-out in this work is the critical step towards product relevant assessment of ultra-thin gate oxides.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Voltage stress-induced hot carrier effects on SiGe HBT VCO

This paper presents the hot carrier (HC) induced performance degradation in a 10 GHz voltage controlled oscillator (VCO) with SiGe heterojunction bipolar transistors (HBTs). SiGe device characteristics due to HC stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured data are used in Cadence SpectreRF simulation to verify the HC effect on the VCO. The VCO shows significant vulnerability to hot carriers.     

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.     

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO₂ gate dielectrics and n⁺⁺ or p⁺⁺ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p⁺⁺ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n⁺⁺ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.     

Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide

The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode.     

Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies

A review of the channel hot carrier (CHC) mechanism and its effects on n-MOSFET devices of deep submicron CMOS bulk technologies is presented. Even with power supply reduction (V_supply ≈ 1.0 V) CHC effects still limit aggressive transistor scaling. In this work it is shown that the “Lucky Electron Model” picture is not adequate to describe carrier heating under quasi ballistic transport. A more general physical picture is proposed, in which the driving force of the hot carrier damage is the “carrier dominant energy” determined by the energy convolution of the effective interface states generation (ISG) cross section (S_IT(E)) and the electron energy distribution function (EEDF) at given bias stress conditions. Both the CHC LEM and the energy driven approximations are derived. The latter is shown to be more adequate to describe the CHC degradation with supply voltage reduction. This approach allows an experimental quantification of S_IT(E).