Monolithic fabrication of 2 × 2 crosspoint switches inInGaAs-InAlGaAs multiple quantum wells using quantum-well intermixing

In this letter, we report the fabrication of 2 × 2 crosspoint switches, which monolithically integrate passive waveguides, electro-absorption modulators and optical amplifiers onto one chip using sputtered SiO₂ quantum-well intermixing technique. The switches have low insertion loss to be about 4-5 dB and extinction ratios up to 26 dB     

SiO2/聚合物Y分支波导型热光开关研究

为提高波分复用(WDM)光通信网中核心器件光开关 的响应速度,设计并制备了SiO₂/聚合物复合型 Y分支结构波导热光开关。器 件选择具有高热导率的SiO₂作为波导的下包层,低成本的聚甲基丙烯酸甲脂-甲基丙烯酸 环氧丙酯共聚物(P(MMA-GMA))作为芯层和上包层,利用束 传播法模拟和优化Y分支波导的设计,通过光刻、刻蚀和蒸发等传统半导体工艺进行器件制 备。实验测得开关插入损耗为12dB, 消光比为18dB,方波驱动的上升和下降响应时间均为200μs。实验结果表明,SiO₂/聚 合物复合波导结构可有效提高热场的扩散速度和折射率调节效率,减小开关的响应时间。     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

GaAs MIS structures with SiO2 using a thin siliconinterlayer

The introduction of a pseudomorphic Si interlayer, about 1.0 nm thick, is found to dramatically improve the MIS characteristics of the SiO₂-GaAs system. Quasistatic and high-frequency capacitance/voltage data from such a novel capacitor structure on n -GaAs indicate that the surface of the GaAs is swept from inversion to accumulation. X-ray photoelectron spectroscopy and ion scattering spectroscopy confirm the presence of the Si layer and its complete coverage of the GaAs surface. The Si layer minimises the formation of any detrimental native oxides and thus controls the chemical nature of the GaAs surface. This approach has implications in the development of metal-insulator-semiconductor systems in general     

二氧化硅纳米花的制备及发光特性研究

采用磁控溅射和化学气相沉积技术制备出二氧化硅纳米花。利用扫描电子显微镜(SEM),X射线光电子能谱(XPS)和傅里叶红外吸收谱(FTIR)对上述纳米结构进行结构表征。用荧光光谱仪(PL)对其光致发光特性进行了研究。结果表明在激发波长为325nm时,在394nm处出现一个发光峰,表现出良好的发光特性。     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Dry plasma etching of sub-micron structures in a SiO₂/Si/SiO₂ layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O₂, SF₆, CF₄, c-C₄F₈, CHF₃, using DC bias data sets. Application of the c-C₄F₈/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97 nm/min, respectively, while the average SiO₂/Si/SiO₂ to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C₄F₈/90%Ar plasma with optimized parameters.     

Pigtailed tree-structured 8×8 LiNbO3 switch matrixwith 112 digital optical switches

We report on integrated optics Ti:LiNbO₃-based 8×8 switch matrices. The matrix design uses a tree structure with 112 digital optical switches as switch elements. The matrix, which has been pigtailed and packaged in an open package for convenient system demonstrator use, exhibits a worst case insertion loss of less than 15 dB     

Fabrication of thin film transistors using a Si/Si1-xGex/Si triple layer film on a SiO2 substrate

A novel approach that can reduce the thermal budget in the fabrication of thin film transistors (TFTs) using a Si/Si_0.7Ge_0.3/Si triple film as an active layer was proposed. The crystallization behavior of the triple film was described and device characteristics of Si/Si_0.7Ge_0.3 /Si TFTs were compared with those of Si TFTs and of SiGe TFTs. The triple film was completely crystallized only after a 25-h anneal at 550°C. N-channel polycrystalline Si/Si_0.7Ge_0.3/Si TFTs had a field-effect mobility of 57.9 cm²/Vs and an I_on/I_off ratio of 5.7×10⁶. This technique provides not only a shorter time processing capability than Si TFT's technology but also superior device characteristics compared to SiGe TFTs     

Determination of Si/SiO2 interface roughness using weaklocalization

The interface roughness of intentionally textured Si/SiO₂ interfaces was measured using the quantum weak localization (WL) correction to the electrical conductivity at low temperatures. The deduced roughness was confirmed by observation of the Si surface replicas by atomic force microscopy (AFM). Quantitative agreement between the two methods was found (Δ=1.2 to 1.4 Å from WL and 1.35 Å from AFM). For a surface with artificially induced texture, it is found that WL can easily distinguish a significant increase in roughness relative to the smooth surfaces. AFM confirms this qualitative conclusion     

TiO_2/SiO_2、ZrO_2/SiO_2多层介质膜光学损耗及激光损伤研究

以TiO_2/SiO_2及ZrO_2/SiO_2多层介质膜为例,测试了不同工艺条件及不同膜系结构下薄膜样品的光学损耗及激光损伤阈值,同时对实验结果作了初步的分析讨论.     

Fabrication of SiO2 microdisk arrays for optics and light trapping experiments

We present a simple silicon based microfabrication process that produces an array of SiO₂ microdisks using UV lithography. High-resolution SEM images of these structures indicate a smooth outer microdisk cavity surface. Photoemission measurements were performed at different spots on the microdisk and compared with measurements inside the cavity. A silicon to oxygen atomic concentration ratio of 1:2 obtained during depth profiling confirms that the entire microdisk is made up of stoichiometric SiO₂. In contrast, the inner cavity is mostly silicon with native oxide on top. We discuss the usefulness of SiO₂ microdisks in optics for light trapping experiments.     

Adiabatic 2×2 polarization splitter on LiNbO3

The authors have demonstrated a passive 2×2 polarization splitter in x-cut LiNbO₃, using a hybrid Ti-indiffusion/proton-exchange technology. At a wavelength of 1530 nm, all paths exhibited an extinction ratio of better than 20 dB, with an average excess loss of 1 dB. This component can be integrated with optical filters, switches, and beam combiners to achieve polarization-independent operations     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

Hot-carrier injections in SiO2

We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (< 5 nm) gate-oxide.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

Accelerated testing of SiO2 reliability

This paper compares several popular accelerated test methods for projecting SiO₂ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q_BD test for extraction of the defect distribution. Measurement issues are also discussed     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.