A versatile 700-1200-V IC process for analog and switchingapplications

An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200-V LDMOS and 700-V LIGBT (lateral insulated-gate bipolar transistor), as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given     

A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

Implementing IC based designs for 3.3-V supplies

Many of today's VLSI chips operate at 3.3V, ultimately requiring DC-DC converters that are light, small, and ideally, realized in IC technology. Recent developments in switching-mode power supplies, which contain no magnetic devices have the potential to satisfy the above requirements. These supplies contain only switched-capacitor elements in the power stage, a necessary condition for implementing low-voltage power sources with ICs. We present a new architecture using discrete devices that offers significant potential in IC-based supplies     

微型加速计全差分Σ-Δ接口IC

主要描述一种加速度感应系统全差分Σ-ΔCMOS接口IC。电容传感器接口由一个前端可配置开关电容(SC)电荷放大器和一个末端,一阶SCΣ-Δ调制器组成。本设计采用开关双采样技术(CDS)来消减低频噪声,能有效地隔离高性能Σ-Δ调制器和MEMS传感器。采用0.35μm CMOS技术,在3.3 V电源环境下能够理想工作。仿真结果显示该设计能达到0.55 V/g的精度。     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.     

A flat-panel display control IC with 150-V drivers

A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resistivity epitaxial area. A compact complementary transistor logic circuit is successfully integrated in the n-wells of the structure's thin epitaxial area to meet the high-speed requirement for control logic. A stacked circuit is used to reduce the standby power needs of the logic circuits.     

A 1-V heterogeneous reconfigurable DSP IC for wireless basebanddigital signal processing

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm×6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-μm 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network     

A 3.3-V/5-V low power TTL-to-CMOS input buffer

A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applications. It has low power dissipation, high operating speed, and a logic threshold voltage less sensitive to process and supply voltage variations. The proposed SSIB input buffer was realized in a 0.8-μm single-polysilicon double-metal (SPDM) CMOS technology, The measured logic threshold voltage variations due to process variations are ±24 mV for 5 V supply and ±16 mV for 3.3 V supply, respectively. Its logic threshold voltage variations due to supply voltage variation from 3.3 V to 5 V are within 10 mV. In ring oscillator configuration, the measured delay and power dissipation are 0.45 ns and 0.37 mW for 5-V supply and 0.51 ns and 0.14 mW for 3.3-V supply, respectively     

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.     

3.3-V BiCMOS current-mode logic circuits for high-speed adders

New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-μm BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders     

A versatile 250/300-V IC process for analog and switching applications

A true analog high-voltage IC process and related devices are described. The process is based on bipolar low-voltage devices to which have been added 300-V lateral n-MOS and p-MOS transistors with source-follower capability. The present process version includes 250-V vertical DMOS transistors for compact switching of moderate power, whereas 5/20-V CMOS is available for control. Application examples are an 8-MHz video output amplifier and a 20-W full-bridge power switch.     

A 200-V flat-panel display IC with a novel diffused-well structure

A high-voltage diffused-well structure that allows the low-coast fabrication of a monolithic high-voltage CMOS IC without using any epitaxial layers is discussed. Offset-gate-type PMOSTs for the proposed structure were fabricated within an n-well and a breakdown voltage over 200 V was obtained. A high-performance 200-V CMOS test IC for which high-voltage NMOSTs and low-voltage CMOS peripheral circuits were built in the p-type substrate area was fabricated. Superior latchup immunity was obtained with this structure. A 2200-pF capacitance load corresponding to that of an electroluminescent display panel was successfully driven     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A portable digital DLL for high-speed CMOS interface circuits

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-μm standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm²     

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digitalwireless communication

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz f_t silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V     

A high-voltage IC for a transformerless trunk and subscriber line interface

A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration in transformerless line circuits. The new configuration uses the high-voltage IC plus some low voltage control circuitry to provide limited current battery-feed, loop-closure detection, reverse-battery signaling, two-wire to four-wire conversion, lightning protection, power-down capability, and longitudinal performance which is independent of the battery-feed current magnitude.     

The IC yield problem: A tentative analysis for MOS/SOS circuits

Yield on integrated circuits is the result of the contribution of many parameters including number of masking steps, design dimensions, and intrinsic process steps. Test vehicles specific to each process to be investigated are used and through ring oscillators yield figures, and test pattern results, evaluation of yield, as well as identification of main causes of yield loss can be made. The test vehicle approach is consistent with actual LSI circuits yield figures. Defect densities for SOS and bulk processes are compared showing that they are mainly dependent upon the number of critical masking steps and design dimensions.     

700-V asymmetrical 4H-SiC gate turn-off thyristors (GTO's)

Silicon Carbide (4H-SiC), asymmetrical gate turn-off thyristors (GTO's) were fabricated and tested with respect to forward voltage drop (V_F), forward blocking voltage, and turn-off characteristics. Devices were tested from room temperature to 350°C in the dc mode. Forward blocking voltages ranged from 600-800 V at room temperature for the devices tested. V_F of a typical device at 350°C was 4.8 V at a current density of 500 A/cm². Turn-off time was less than 1 μs. Although no beveling or advanced edge termination techniques were used, the blocking voltage represented approximately 50% of the theoretical value when tested in an air ambient. Also, four GTO cells were connected in parallel to demonstrate 600-V, 1.4 A (800 A/cm ²) performance     

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.