Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Scaling-parameter-dependent model for subthreshold swing S indouble-gate SOI MOSFET's

We derived a simple formula for the subthreshold swing S in double-gate (DG) SOI MOSFET's. Our formula, which depends only on a scaling device parameter, matches the device simulation results. From these results, our equations are simple and give a scaling rule for DG-SOI MOSFET's     

Dominant subthreshold conduction paths in short-channel MOSFET's

Conduction modes in off-biased n⁺-polysilicon gate MOSFET's of both polarities have been analyzed by two-dimensional device simulations. It was found that the dominant leakage paths in p-channel and n-channel enhancement devices occur in the bulk and at the surface, respectively, atV_{GS} = V_{BS} = 0. The control of these two distinct modes is the flatband voltage of the gate. The situation is exactly reversed when boron-doped polysilicon is used as the gate. Additionally, we showed that this physical insight can be readily gained by a quasi-two-dimensional analysis of the surface potential and its bending into the substrate. The leakage mode in short-channel MOSFET's with other gate material or with different interface properties generated by radiation or other stresses can thus be easily assessed. Subthreshold characteristics have been simulated for n⁺-polysilicon-gate low-threshold p-channel transistors having a p-type surface from boron counterdoping. The computed channel-length dependence is found to be in good agreement with measured data. Dominant leakage paths, in this case, remain in the bulk, while the surface holes from boron counterdoping are depleted by the flatband voltage. Since the common practice for reducing subthreshold leakage is to enhance substrate impurity concentration where punchthrough occurs, we therefore conclude that different strategies of process tailoring are required for MOSFET's of different gate material, surface polarity, and interface properties.     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Substrate bias dependence of subthreshold slopes in fully depletedsilicon-on-insulator MOSFET's

Subthreshold slopes in submicrometer n-channel MOSFETs in depleted silicon-on-insulator (SOI) films were measured as a function of substrate bias and temperature, as well as drain bias. It is found that for low drain voltage, a simple capacitor model can explain the result. For large drain voltages, anomalously sharp threshold slopes are observed for very negative substrate biases, but the anomalous effects are greatly reduced with a more positive substrate bias. A qualitative model based on the charge state of the lower SOI interface is proposed to explain the dependence of the anomalous effects on substrate bias     

A model for PolySilicon MOSFET's

A model is developed to describe the high value of threshold voltage and the low value of channel mobility observed in n-channel polysilicon (poly-Si) MOSFET's. The model takes into account charge-coupling between the gate and grain boundary traps. The charge-coupling appears as an image charge in Poisson's equation and the charge neutrality equation. Finally, a drift-diffusion mode of conduction is used to describe the channel conductance beyond the strong inversion threshold.     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

A simple punchthrough model for short-channel MOSFET's

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10¹⁴and 6.6 × 10¹⁵cm^-3and channel lengths from 1 to 2 µm show good agreement with the theory.     

A simple model for short channel MOSFET's

A model for short channel MOSFET's is presented. The model is simple in spite of taking 2-dimensional (2-D) effects into account. Predicted I-V characteristics are in good agreement with experimental results. This model can be utilized in circuit analysis programs.     

A spillover effect of avalanche-generated electrons in buriedp-channel MOSFET's

The authors describe a new mechanism for hot-electron resistance in buried p-channel MOSFETs, which is explained by the spillover of avalanche-generated electrons into the bulk. This effect was observed in a buried p-channel MOSFET formed in a retrograde n-well. It is shown that this effect reduces the hot-electron-induced device degradation even with the greater number of avalanche-generated electrons induced by high bulk doping     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

A subthreshold current model for GaAs MESFET's

A GaAs MESFET model capable of accurately describing currents in the subthreshold region is described. The model is based on the concept of drain-induced barrier lowering (DIBL) together with the reverse-bias Schottky diode conduction. Agreement between measured and calculated data based on this model was excellent.     

A simple model for threshold voltage of surrounding-gate MOSFET's

We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

Transit-time model for short-channel MOSFET's

A new analytical transit-time model for submicrometer MOS devices has been developed. The model is based on a modified SPICE level-three MOSFET DC model, and it allows the use of a physical value for the charge carrier saturation velocity. This is essential for accurate transit-time modeling. Both DC and transit-time models show good agreement with the results obtained from more complicated two-dimensional numerical simulations     

Unified physical I-V model including self-heating effect for fullydepleted SOI/MOSFET's

A physically based analytical I-V model that includes self-heating effect (SHE) is presented for fully depleted SOI/MOSFET's. The incorporation of SHE is done self-consistently in a fully closed form, making the model very suitable for use in circuit simulators. The model also accounts for the drain induced conductivity enhancement (DICE) and drain induced barrier lowering (DIBL), channel length modulation (CLM), as well as parasitic series resistances (PSR). Another advantage is the unified form of the model that allows us to describe the subthreshold, the near-threshold and the above-threshold regimes of operation in one continuous expression. A continuous transition of current and conductance from the linear to the saturation regimes is also assured. The model shows good agreement with measured data for a wide range of channel lengths (down to 0.28 μm) and film thicknesses (94 nm-162 nm)     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.