Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

FPGA设计中的亚稳态研究

探讨了亚稳态的产生机制,对FPGA设计中的亚稳态进行分析,针对FPGA设计中的亚稳态问题,给出了一系列行之有效的解决方法.提供的设计技巧和优化手段在实践中可以很好地抑制亚稳态,提高系统可靠性.     

Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters

We present a theory for metastability error power in SuccessiveApproximation A/D converters. The traditional measure, BER, does not accountfor the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and aSignal-to-Metastability-error-Ratio, SMR, is suggested as a new measure. Suppressing SMR below SNR imposes a gain requirement on the comparator.     

Metastability tests of flip-flops in programmable digital circuits

This paper describes the methods and experimental techniques for determination of the metastability behavior of the flip-flops used in the programmable digital circuits. A dual model of the metastability distinguishes two transitions at the flip-flop output (L/H and H/L) which have different impact on the Mean Time Between Failures (MTBF) of the flip-flop. A new circuit of the late transition detector (LTD) allows for determination of the pairs of the metastability parameters, the window W and the time constant τ, for both transitions. The test results are presented for four types of programmable digital circuits fabricated commercially in CMOS technology. In the all tests, the H/L transition clearly dominates with respect to MTBF (as a worse one). The presented test methods can also be used for evaluation of flip-flops in nonprogrammable digital circuits.     

A device architecture for computing with quantum dots

We describe a paradigm for computing with interacting quantum dots, quantum-dot cellular automata (QCA). We show how arrays of quantum-dot cells could be used to perform useful computations. A new adiabatic switching paradigm is developed which permits clocked control, eliminates metastability problems, and enables a pipelined architecture     

Flash A/D转换器中火花码与亚稳态现象研究

全并行模数转换器(FlashA/D转换器)结构简单,转换速度快,但电路规模较大,精度受到限制.FlashA/D转换器具有"亚稳态","火花码"等非理想特性,严重的影响了它的工作性能.本文较系统地介绍和分析了已有的一些抑制"火花码"与"亚稳态"的方法.并提出一种基于概率统计的算法,通过SIMULINK软件进行仿真,对各种编码电路对输出误码率的影响进行了研究和量化对比,结论表明wlallace Trec编码结构对"火花码"及"亚稳态"的抑制能力最强.     

A fast resolving BiNMOS synchronizer for parallel processorinterconnect

The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer     

Miller and noise effects in a synchronizing flip-flop

The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T_m and τ. The flip-flop was fabricated on a 0.25-μm CMOS process     

一种用于高可靠性同步器电路的D 触发器设计

随着VLSI设计的发展，设计师时常需要面临不同时钟域之间信号传输和异步复位／置位等情况，在这类情况下，电路就有可能出现亚稳态。以及处理亚稳态的一种解决方案，D触发器在亚稳态下的特性。提出了一种减少亚稳态出现可能性的D触发器单元的设计方案，并使用H－SPICE进行了仿真。     

Burst error generator using flip-flop metastability

A novel burst error generator for communications systems testing is presented which is based on the phenomenon of metastability observed in flip-flops. Bursts can be created with predetermined bit error ratios by means of an external control voltage. The errors appear to follow a double Poisson distribution, characteristic of the Neyman type A contagious process     

Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Nowadays, metastability is becoming a serious problemin high-performance VLSI design, mainly due to the relatively-highprobability of error when a bistable circuit operates at highfrequencies. As far as we know, there is not any work publishedthat justifies and formally characterizes metastable behaviorin dynamic latches. With current technologies, dynamic latchesare widely used in high-performance VLSI circuits, mainly dueto their lower cost and higher operation speed than static latches.In this work, we demonstrate that dynamic memory cells presentan anomalous behavior referred to as metastable operation withcharacteristics similar to those of static latches. We performa suitable generalization of metastability to the dynamic case,applying it to a CMOS dynamic D-latch. A theoretical model willbe proposed, allowing the quantification of metastability, andit will be validated through electric simulation with HSPICE.After that, we have compared the metastable behavior of the dynamiclatch with its static counterpart, obtaining results about thecharacteristic parameters of metastability and the Mean TimeBetween Failures (MTBF) for both kinds of bistable circuits.These results have allowed us to conclude that, unlike metastabilitywindows in static latches, a clearly defined input interval existswhich produces an infinite resolution time. Regarding MTBF, thedynamic latch presents a very low MTBF value compared to thestatic latch. These results show that dynamic latches shouldnot be used in those circuits where the risk of asynchronismbetween clock and data signals is not negligible.     

Auto-tuned counter synchronisation in FPGA-based interpolation time digitisers

A novel method for auto-tuned synchronisation of the counter in interpolation time digitisers is described. A clock phase adjustment is utilised to avoid the metastability effect in the counter and to achieve the highest possible operating frequency in a given technology.     

多时钟域数据传递的FPGA实现

分析了多时钟域数据传递设计中亚稳态的产生以及对整个电路性能和功能的影响,以一款异步并行通信接口芯片的设计为例,详细描述了采用同步器、FIFO实现8位并行数据到16位并行数据的两时钟域异步转换的过程。电路在XilinxISE6.0环境下用Modelsim5.7进行了逻辑仿真,结果表明系统稳定可靠。     

Metastability of SOI CMOS latches

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time t _meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies.     

Characterization of a Flip-Flop Metastability Measurement Method

We characterize a proposed metastability measurement system in which asynchronous data input and sampling clock frequencies trigger metastability. We develop an equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these values. Finally, we present experimental results supporting our characterization     

Comments, with reply, on `Metastability of CMOS latch/flip-flop'

For the original article see ibid., vol.25, no.4, pp.942-951 (Aug. 1990). In the above titled paper L.-S. Kim and R.W. Dutton used SPICE small-signal circuit simulation (SPICE AC command) to evaluate a metastability performance parameter, τ, and compared several latch and flip-flop designs. They suggest that small-signal simulation is much easier to carry out than large-signal simulation for metastability studies and can be used to predict metastability performance. However, small-signal simulation is not sufficient to characterize metastability performance since it cannot determine a second parameter which is needed to determine synchronizer failure probability. In addition, Kim and Dutton make several errors in their use of small-signal simulation for determination of τ. The commenters present their own results that contrast with the original paper's conclusions, and discuss additional methods for determining τ. In their reply, Kim and Dutton acknowledge the commenters' points and go on to focus on how AC analysis can be used to extract the second parameter mentioned in the comment     

Metastability of CMOS latch/flip-flop

Optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops are obtained by using the AC small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) was measured, and the result verifies this new design approach. The power supply disturbance and temperature variation effects on the metastability were also measured, and the data show that a 0.75-V change of power supply voltage and 75°C change of chip temperature cause a four orders of magnitude difference in the MTBF. The simulation results using the AC small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures, confirming that an AC small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. The other parameters are discussed in terms of their effects on the latch/flip-flop's susceptibility to the metastable state     

多时钟域的异步信号的参考解决

在ASIC设计中,不同的模块往往工作在不同的频率下,在一个芯片上采用单时钟设计基本上是不可能实现的。多时钟域的设计是SOC设计中的一个重要环节。分析了多时钟域设计中异步信号的产生以及带来的亚稳定性对整个电路性能和功能的影响,提出了采用同步器,握手通信协议,FIFO等方法减小亚稳定性概率和其影响的措施,并且给出了实用电路图并进行了实现,从而使得电路能够在多时钟域下更加健壮和稳定。     

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V_CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal V_CC or at least 17% V_CC reduction at equal throughput, corresponding to 31%-37% total power reduction.     

From synchronous to GALS: A new architecture for FPGAs

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.