Novel merged BiCMOS circuit structures

Novel merged BiCMOS circuit structures are presented. They offer an area saving of 20-30% compared with conventional BiCMOS structures. The DC and the transient performance of the merged structures are verified using the two-dimensional PISCES-IIB device simulator.<>     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

High speed BiCMOS current mode differential track-and-hold circuit

A new principle for a high speed BiCMOS differential track-and-hold circuit based on current mode processing is presented, and simulation results are given. The main characteristics are an acquisition time of 5.5 ns for 8 bit precision and a small-signal bandwidth of 1 GHz     

BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

Novel circuits for high speed ROMs

Novel approaches in circuit design, such as overlap timing without precharge, complementary ROM cells with two access lines, and overall chain-delay optimization, greatly increase the operational speed of ROMs. The innovative circuits fabricated with an advanced CMOS/SOS process resulted in an experimental 18-kbit (2K/spl times/9) look-up ROM performing a cycle time of 4 ns, a silicon area of 7.2 kmil/SUP 2/ and a radiation hardness of >10/SUP 5/ rad(Si). The overlap timing can multiply the address and data change rate without reducing the overall chain delay. The utilization of complementary ROM cells increases data processing speed, noise margin, and radiation hardness. The overall chain delay is greatly reduced by finding the minimum of a device size dependent time function. The complementary cell features a size of 12/spl times/17.2 /spl mu/m, shared contacts, and tantalum polycide access lines. The circuits discussed here can be used for any high-speed memory design, although the demonstration vehicle is a CMOS/SOS ROM.     

A BiCMOS PLL-based data separator circuit with high stability andaccuracy

A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2-μm BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

一种运用于高速ADC的采样保持电路设计

设计了一种用于Pipelined ADCs中的前置采样保持电路.从理论上推导了12bit、100MHz的模数转换器对采样保持电路各个子电路的性能指标要求,按此要求设计了增益增强型运放、自举开关等子电路.基于SMIC 0.13μm,3.3V工艺,Spectre仿真结果表明,在采样频率为100MS/s,输入信号频率为9.7656M时实现了81.9dB的信噪失真比(SINAD)和13.3位的有效位数(ENOB),无杂散动态范围(SFDR)可达94.9dB,功耗仅为24mW.输入直到奈奎斯特频率,仍能保持81.5dB的信噪失真比和13.2位的有效位数,SFDR可达到92.67dB.     

A high speed GaAs error-detection circuit for fiber-optictransmission systems

A high-speed GaAs IC for detection of line code vibrations is described. This 144-gate error-detection circuit for monitoring a high-bit-rate fiber-optic link has been designed and fabricated using a high-yield titanium tungsten nitride self-aligned gate MESFET process. This process routinely provides a wafer-averaged gate delay (fan-in=fan-out=2) of less than 70 ps with a power dissipation of 0.5 mW/gate. The error-detection circuits were tested on-wafer using high-frequency probe cards at a clock rate of 1.4 GHz, with a yield of 64%. Packaged circuits worked at a clock frequency of over 2.5 GHz and consumed 200-mW power at a fixed power supply voltage of 1.5 V. The circuits operate over a wide variation in power supply voltage and temperature. When operated at a package temperature of 125°C, the circuits show less than a 12% degradation in their maximum clock frequency. The circuit was inserted into a 565-Mb/s system currently using a silicon ECL part, and full functionality was verified with no necessary modifications     

Analysis of the switching speed of BiCMOS buffer under high current

A nonlinear analytical transient response model that is suitable for BiCMOS driver circuits operating under the Kirk and Van der Ziel effect is presented. The model accounts for both base vertical push-out and lateral stretching phenomena where the forward transit time τ _f has a square law dependence on the collector current. Based on the new transient model, a closed-form BiCMOS delay expression is derived that shows excellent agreement with measured gate delay from a 0.8-μm BiCMOS technology. The comparison is made for a wide range of circuit parameters. The delay model can be used to develop timing analyzers, timing simulators, and circuit optimization tools for ULSI circuit design. As an application of the delay model, a circuit design algorithm is derived to optimize the speed-area performance of the BiCMOS buffers     

新型高速电光调制器

介绍了目前高速长距离光纤通信中常用的电光调制器的原理、结构和应用．目前半导体调制器的研究日趋成熟，性能不断改善．有机聚合物电光调制器被公认为是最具潜力的高速光通信调制器，正成为人们关注的焦点．     

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted     

一款适用于高速读出电路的输出级运算放大器设计

〖JP+1〗CMOS运算放大器是红外探测器系统读出电路的重要模块,其性能直接影响红外读出电路性能。本文设计了一款适用于高速读出电路的输出级运算放大器,在负载电阻100 kΩ,负载电容25 pF的条件下,使读出电路的工作频率大于20 MHz。输出级运算放大器由折叠共源共栅差分运放和甲乙类推挽反相运放级联构成。折叠共源共栅差分运放可以实现电路高增益、大输出电压范围和高输出阻抗,同时可以有效减小放大器输入端的米勒电容效应。甲乙类推挽反相运放具有高电压电流转换效率,可以灵活地从负载得到电流或者向负载提供电流,实现高电流增益,驱动大负载。两级运放之间通过米勒电容实现频率补偿,保证运放的稳定性。本文设计的高速输出级运算放大器基于SMIC 018μm工艺设计,最终实现指标:功耗不大于10mW,运放增益>84dB,相位裕度79°,单位增益带宽>100 MHz,噪声78 μV(1～500 MHz),输出电压范围1～5 V,建立时间<15ns。通过设计高速输出级运算放大器,红外读出电路的读出速率和帧频得到有效提高。     

SOI-DRAM circuit technologies for low power high speed multigigascale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty     

Comparison of high speed DI-LIGBT structures

The performance of the DI segmented collector (SC)-LIGBT is compared to the collector shorted (CS)-LIGBT. The SC-LIGBT allows for adjusting the tradeoff between switching speed and on-state voltage drop by simply changing the P⁺ collector segment width during device layout. In contrast to previously reported junction isolated (JI) devices, the DI SC-LIGBT was observed to have a turnoff speed similar to the CS-LIGBT with a higher forward drop than the conventional LIGBT. The on-state performance of the integral diodes of the SC-LIGBTs was found to be superior to the integral diode of the CS-LIGBT. The integral diodes of both the CS and the SC-LIGBTs were found to have much superior switching characteristics compared to a lateral PiN diode at the expense of a higher on-state voltage drop. Thus, the superior switching characteristics of the integral diode in the SC-LIGBT complements its fast switching behavior making this device attractive for compact, high frequency, high efficient, power ICs.     

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity     

高速数字电路中的信号完整性分析

在高速数字电路设计中,随着电子产品的不断更新换代,其系统主频变得越来越高和产品变得越来越小型化,板级互连线的信号完整性问题也越来越突出。针对高速数字电路设计中的反射和串扰等信号完整性问题,分析破坏信号完整性的原因,并提供改善信号完整性的方法：采用端接技术和增加敏感信号线的间距。通过采用Hyperlynx仿真工具对在SC...