A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time andmemory-cell area efficiency of 33%

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage     

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.<>     

8-ns CMOS 64 K×4 and 256 K×1 SRAMs

SRAMs (static random-access memory) with a 64 K×4 and 256 K×1 structure and with 8-ns access time have been developed on a 1.0-μm CMOS process. Circuits are designed with source-coupling techniques to achieve high speed with small signal swings, using only CMOS devices. A metal option permits selection of the 64 K×4 or 256 K×1 configuration. The same core architecture has also been used to generate ×8 and ×9 designs. An output-enable (OE) version achieves 3-ns response time. As system speeds have recently increased toward 100-MHz operation, the need for address transition detection (ATD) has diminished as a means for improving the SRAM speed/power ratio. This trend in SRAM design stems mainly from the fact that AC current becomes the most significant fraction of the total current. Accordingly, the design described here employs a purely static path through the entire SRAM, with no requirement of ATD at any point. The resulting DC current is countered with a combined strategy of array subdivision, small-signal techniques, and active preamplification at key points in the data path     

A CMOS four-channel×1K time memory LSI with 1-ns/b resolution

A four-channel 1024-b time-to-digital converter chip, which records input signals to memory cells at 1-ns intervals, has been developed. To achieve 1-ns precision, the chip incorporates a feedback stabilized delay element. The chip was fabricated on a 5.0-mm×5.6-mm die using 0.8-μm CMOS technology. It dissipates only 7 mW/channel under typical operating conditions     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers     

An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phaseclocked logic-flip-flops

An 8-b adder composed of carry-increment full adders has been designed and implemented in a standard 1.0 μm CMOS technology and successfully tested up to 800 MHz. The performance of this adder is based on a fine-grain pipeline technique using so called “logic-flip-flops”. These edge triggered logic-flip-flops are true single-phase clocked and reduce the cycle time of pipeline stages by combining logic and storage. For low power applications, the power consumption of the 8-b adder can be reduced from 777 mW (5 V Vdd, 800 MHz) down to 144 mW (3 V Vdd, 480 MHz)     

A 40–50-GHz SiGe 1 : 8 Differential Power Divider Using Shielded Broadside-Coupled Striplines

This paper presents a 1 : 8 differential power divider implemented in a commercial SiGe BiCMOS process using fully shielded broadside-coupled striplines integrated vertically in the silicon interconnect stackup. The 1 : 8 power divider is only 1.12 $,times,$1.5 mm$^{2}$ including pads, and shows 0.4-dB rms gain imbalance and $≪ {hbox{3}}^{circ}$ rms phase imbalance from 40 to 50 GHz over all eight channels, a measured power gain of ${hbox{14.9}} pm {hbox{0.6}}$ dB versus a passive divider at 45 GHz, and a 3-dB bandwidth from 37 to 52 GHz. A detailed characterization of the shielded broadside-coupled striplines is presented and agrees well with simulations. These compact lines can be used for a variety of applications in SiGe/CMOS millimeter-wave circuits, including differential signal distribution, miniature power dividers, matching networks, filters, couplers, and baluns.