单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管

介绍了单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管（PHEMT）工艺。借助栅金属的热处理过程,形成了热稳定性良好的Pt／Ti／Pt／Au栅。AFM照片结果表明Pt金属膜表面非常平整,2nm厚度膜的粗糙度RMS仅为0．172nm。通过实验,我们还得出第一层Pt金属膜的厚度和退火后的下沉深度比大概为1：2。制作的增强型／耗尽型PHEMT的闽值电压（定义于1mA／mm）、最大跨导、最大饱和漏电流密度、电流增益截止频率分别是＋0．185／-1．22V、381．2／317．5mS／mm、275／480mA／mm、38／34GHz。增强型器件在4英寸圆片上的阈值电压标准差为19mV。     

Performance dependence of InGaP/InGaAs/GaAs pHEMTs on gatemetallization

The performance of InGaP-based pHEMTs as a function of gate metallization is examined for Mo/Au, Ti/Au, and Pt/Au gates. DC and microwave performance of pHEMT's with 0.7-μm gate lengths is evaluated. Transconductance, threshold voltage, f_t, and f_max are found to depend strongly on gate metallization. High-speed performance is achieved, with f_t of 41.3 GHz and f _max of 101 GHz using Mo/Au gates. The difference in performance between devices with different gate metallizations is postulated to be due to a combination of the difference in Schottky barrier heights and different gate-to-channel spacings due to penetration of the gate metal into the InGaP barrier layer     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT with asilicon interface control layer showing high DC- and RF-performance

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 μm. As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f_T, of 9 GHz and the maximum oscillation frequency, f_max, of 38 GHz were obtained for the 1.6 μm-gate-length device     

0.3-μm gate-length enhancement mode InAlAs/InGaAs/InPhigh-electron mobility transistor

The fabrication and performance of ultra-high-speed 0.3-μm gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent threshold voltage uniformity have been achieved. The devices demonstrate a threshold voltage of +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extrinsic transconductance of 697 mS/mm is measured at room temperature. The output conductance is 22 mS/mm, which results in a maximum voltage gain (g_m/g₀ ) of 32. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f_t) of 116 GHz and a maximum frequency of oscillation (f_max) of 229 GHz. To the best of the authors' knowledge, these are the highest reported frequencies for lattice-matched E-HEMT's on InP     

Gate-length dependence of DC and microwave properties ofsubmicrometer In0.53Ga0.47As HIGFETs

In_0.52Al_0.48As/In_0.53Ga_0.47 As/InP heterostructure insulated-gate field-effect transistors (HIGFETs) with gate lengths from 1.1 and 0.3 μm have been fabricated, and their electrical performance is characterized at DC and microwave frequencies. The refractory-gate self-aligned process, applied to devices with In_0.53Ga_0.47As channels, yields an unprecedented combination of very-high speed and excellent uniformity. HIGFETs with L_g=0.6 μm showed average peak transconductance g_m of 528 mS/mm and unity-current-gain cutoff frequency f_t of 50 GHz. The uniformity of g_m was better than 1%, and the voltage of the g_m peak was uniform to ±30 mV. HIGFETs with L_g=0.3 μm showed f₁ up to 63 GHz, but suffered from serious short-channel effect, due to excessive thickness of the InGaAs channel layer. A self-aligned technique for gate resistance reduction is shown to substantially improve microwave power gain     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

InP-based enhancement-mode pseudomorphic HEMT with strainedIn0.45Al0.55As barrier andIn0.75Ga0.25As channel layers

Using strained aluminum-rich In_0.45Al_0.55As as Schottky contact materials to enhance the barrier height and indium-rich In_0.75Ga_0.25As as channel material to enhance the channel performance, we have developed InP-based enhancement-mode pseudomorphic InAlAs/InGaAs high electron mobility transistors (E-PHEMT's) with threshold voltage of about 170 mv. A maximum extrinsic transconductance of 675 mS/mm and output conductance of 15 mS/mm are measured respectively at room temperature for 1 μm-gate-length devices, with an associated maximum drain current density of 420 mA/mm at gate voltage of 0.9 V. The devices also show excellent rf performance with cutoff frequency of 55 GHz and maximum oscillation frequency of 62 GHz. To the best of the authors' knowledge, this is the first time that InP-based E-PHEMT's with strained InAlAs barrier layer have been demonstrated     

0.15-$muhboxm$-Gate InAlAs/InGaAs/InP E-HEMTs Utilizing Ir/Ti/Pt/Au Gate Structure

High-current 0.15-mum-gate enhancement-mode high-electron mobility transistors utilizing Ir/Ti/Pt/Au gate metallization were fabricated using a new process including a high-temperature gate anneal that is required for Schottky-barrier height enhancement for the Ir-based gate contact. SiN_x encapsulation was employed to prevent thermal degradation of device layer during the high-temperature gate anneal. Excellent enhancement-mode operation, with a threshold voltage of 0.1 V and I_DSS of 2.1 mA/mm, was realized. Both the annealed and unannealed devices exhibited high g_m,max and I_D,max of 800 mS/mm and 430 mA/mm, respectively. A unity current-gain cutoff frequency f_T of 151 GHz and a maximum oscillation frequency f_MAX of 172 GHz were achieved. From the dc and RF characteristics, it can be deduced that there was no degradation of the gate contact and the heterostructure due to gate annealing. Furthermore, it was found that the gate diffusion during gate annealing was negligible since no increase in g_m,max was observed     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

Optimization of gate-to-drain separation in submicron gate-lengthmodulation doped FET's for maximum power gain performance

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g_m/g_o), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c_oμ_n product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g_m/g_o ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f_r) and the maximum frequency of oscillations (f _max) on the gate-to-drain separation (L_gd). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 μm, 0.15 μm and 0.1 μm are considered for analyses. The optimum values of L_gd calculated are 600 Å, 420 Å, and 340 Å for the corresponding maximum f_max-values of 250, 370, and 480 GHz, respectively     

Fabrication of depletion-mode GaAs MOSFET with a selectiveoxidation process by using metal as the mask

The n-channel depletion-mode GaAs MOSFETs with a selective liquid phase chemical-enhanced oxidation method at low temperature by using metal as the mask (M-SLPCEO) are demonstrated. The proposed process can simplify one mask to fabricate GaAs MOSFET and grow reliable gate oxide films as well as side-wall passivation layers at the same time. The 1 μm gate-length MOSFET with a gate oxide thickness of 35 nm shows a transconductance of 90 mS/mm and a maximum drain current density larger than 350 mA/mm. In addition, a short-circuit current gain cutoff frequency f_T of 6.5 GHz and a maximum oscillation frequency f _max of 18.3 GHz have been achieved from the 1 μm×100 μm GaAs MOSFET     

Selectively dry-etched n+-GaAs/N-InAlAs/InGaAs HEMTs forLSI

High-speed n-InAlAs/InGaAs HEMT large-scale integrated circuits must have uniform device parameters. A selectively dry-etched n⁺ -GaAs/N-InAlAs/InGaAs HEMT which has a very uniform threshold voltage is discussed. Despite the high dislocation density at the n⁺-GaAs layer, its performance is excellent. For a gate length of 0.92 μm, the maximum transconductance of the HEMT is 390 mS/mm. The measured current-gain cutoff frequency is 23.7 GHz, and the maximum frequency of oscillation is 75.0 GHz. The standard deviation of the threshold voltage across a 2-in wafer is as low as 13 mV     

Temperature-dependent nonlinearities in GaN/AlGaN HEMTs

Temperature-dependent nonlinearities of GaN/AlGaN HEMTs are reported. The large-signal device model of the transistor is obtained by using a physics-based analysis. The model parameters are obtained as functions of bias voltages and temperature. The analysis of the device has been carried out using a time-domain technique. f_max for a 0.23 μm×100 μm Al_0.13Ga_0.87N/GaN FET is calculated as 69 GHz at 300 K, while at 500 K, f_max decreases to 30 GHz, which are in agreement with the experimental data within 7% error. f_max as obtained from calculated unilateral gain, decreases monotonically with increasing temperature. For shorter gate lengths irrespective of the operating temperature f_max is less sensitive to bias voltage scaling. For longer gate length devices, f_max becomes less sensitive to the bias voltage scaling at elevated temperatures. 1-dB compression point (P_1-dB ) at 4 GHz for a 1 μm×500 μm Al_0.15Ga_0.85N/GaN FET is 13 dBm at 300 K. At 500 K, P_1-dB decreases to 2.5 dBm for the same operating frequency. Similar results for output referred third intercept point (OIP3) are reported for different gate length devices     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

A high-current pseudomorphic AlGaAs/InGaAs double quantum-wellMODFET

Double quantum-well modulation-doped field-effect transistors (MODFETs) with planar-doped lattice-strained AlGaAs/InGaAs structure have been fabricated and characterized at DC and microwave frequencies. At 300 K the 0.3-μm gate devices show a full channel current of 1100 mA/mm with a constant extrinsic transconductance of 350 mS/mm over a broad gate voltage range of 1.6 V. Excellent microwave performance is also achieved with a maximum available gain cutoff frequency f _mag of 110 GHz and a current gain cutoff frequency f _r of 52 GHz. A maximum output power of 0.7 W/mm with 30% efficiency is obtained at 18 GHz     

Temperature dependence of gate forward turn-on voltage (Vf) of i-Al0.3Ga0.7As/n-GaAs HIGFET's

Forward gate current-voltage characteristics and their temperature dependence are investigated for i-Al_0.3Ga_0.7As/n-GaAs doped-channel HIGFET's (DC-HIGFET's) with the gate length of 0.3 μm. The temperature coefficient of the gate forward turn-on voltage (Vf) varies with the thickness (t_U) of an i-AlGaAs layer, and shows a minimum value of -0.8~-0.9 mV/deg at t_u=10 nm     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed