Electron image projection systems for microcircuit lithography

High-resolution electron-beam microfabrication requires long process times when using a single scanning beam to expose large-area integrated circuits. Exposure times for a 2-in wafer by a scanning beam system are typically between 30 min to 3 h, depending on the area and complexity of the circuit. This paper describes an electron projection system that projects the whole electron image of the integrated circuit mask onto the wafer at once, enabling exposure times of 1 s or less to be attained. The system incorporates a photocathode patterned into an integrated circuit mask. The pattern is projected and focused onto the wafer using axial magnetic and electrostatic fields. Described herein are factors affecting photocathode life and exposure times. A technique for automatic alignment of the mask to the wafer is also described which has achieved 0.25-µ alignment accuracies.     

Step-and-repeat X-ray/Photo hybrid lithography for 0.3-µm MOS devices

X-ray / photo hybrid lithography is proposed as a method for achieving high resolution and high throughput in sub-half-micrometer VLSI fabrication. Distortions and correction techniques are discussed for accurate registration between X-ray and photo levels. Inherent distortions caused by each type of lithography are measured in advance. These distortions are corrected by introducing a linear shrinkage factor into e-beam data preparation for X-ray mask writing. The overlay accuracy between X-ray and photo levels and also between two X-ray levels is less than 0.15 µm (σ). A three-layer resist system is introduced to fully utilize high-sensitivity and high-resolution features of an X-ray positive resist, FBM-G. An application of hybrid lithography to 0.3-µm MOS devices is presented. The results indicate that further application of X-ray / photo hybrid lithography to the sub-half-micrometer device fabrication process is feasible.     

Determination of wavelength and excitation voltage for X-ray lithography

The exposure time of an X-ray lithography system is minimized by the appropriate choice of X-ray wavelength and target excitation voltage, within the constraints of a specified resolution and contrast in the exposed resist pattern. The factors that must be considered in making this choice are the X-ray source brightness of various target materials, the continuum emission spectrum of the target, the wavelength-dependent transmission of the X-ray mask and the vacuum window, and the wavelength-dependent absorption in the resist. The relative exposure time, as a function of wavelength, is predicted for a system using a 25-µm-thick beryllium window and PMMA resist with three choices of mask substrate: 12.5- µm-thick Mylar, 4.0-µm-thick silicon, and 8.5-µm-thick beryllium. A new mask substrate, 0.2-µm-thick aluminum oxide, is presented and shown to be suitable for exposure in vacuum with a 2.5-µm-thick aluminum filter at 13.3-Å wavelength (copper target). X-ray emission spectra from an aluminum target were measured at electron energies of 4.5, 7.9, 10.4, 12.5, 15.5, 19.5, and 28.5 keV. These spectra showed that the continuum radiation contributes little to the degradation of contrast with a gold-on-silicon X-ray mask. Thus a 20-kV electron beam may be used for maximum X-ray production efficiency.     

A GaAs 16-kbit static RAM using dislocation-free crystal

A GaAs 16-kbit static RAM was developed using high-density integration technology and high-uniformity crystal. Highly integrated SAINT FET's with 1.0-µm gate length and 1.5-µm interconnection lines were formed by self-alignment and fine photolithography. Highly uniform crystal with less than 20-mV threshold scattering was obtained from an In-doped dislocation-free LEC with a 2-in diameter. An address access time of 4.1 ns was obtained with an associated power dissipation of 1.46 W.     

Fabrication of monolithically Peltier-cooled linear laser diodes using wet chemical etching

The basic structure of a monolithically Peltier-cooled laser (MPCL) diode has been fabricated. The process of forming the structure involves critical masking and etching processes. A reliable etching process that was capable of producing clean mesas 50 µm wide × 300 µm long and of a height greater than 150-µm was developed using buffered hydrofluoric acid. The mask used-with the buffered hydro-fluorice etchant was Shipley AZ1350B photoresist. This combination of the etchant and the mask process gave good results even when etching a grid pattern consisting of an array of 2-µm-wide lines to form mesas 3.74 µm high. It was found that the etch tends to follow the cleaved planes that intersect the     

An electron beam maskmaker

An electron beam machine is described, in which the ¼-µm diameter beam is computer controlled to define integrated circuit and other fine patterns at their final size in response to a coordinate data input. Electron sensitive resist is exposed on metallized quartz or glass substrates. Resist development followed by metal etching enables masks to be made, either for subsequent photolithography or, more usually, for use in the electron image projector developed by J. P. Scott. The mask drawing process is entirely automatic and the emphasis is on the rapid generation of complex patterns with high precision. A two-stage deflection system enables rectangular pattern elements to be drawn at a 10-MHz stepping rate and accurately positioned throughout a 2-mm square main deflection field. Patterns are automatically positioned, to an accuracy of ±1/8 µm, relative to an array of markers predeposited on the substrate. The beam is also refocused automatically at the markers. A mechanical stage for the substrate enables 50 × 50-mm arrays of patterns to be built up. A complete mask containing detail as small as 1 µm takes 1-3 h to draw. Finer patterns can be drawn, although more slowly.     

A high current drop GaAs bistable switch

A current drop of 41.5 percent and a switching time of 110 ps is reported for a 10-µm supercritically doped n⁺-n-n⁺GaAs transferred electron device operated as a bistable switch into a 25-Ω resistive load. An investigation to check that no microwave oscillations occur is presented.     

Deep UV 1:1 projection lithography utilizing negative resist MRS

A negative deep UV resist Micro Resist for Shorter wavelengths (MRS) is successfully applied to 1:1 projection printing. The MRS is characterized by strong absorption of deep UV light and absence of swelling in the developer. It resolves steep profile images of 1-µm linewidth in 1-µm-thick films. The resist has extremely high sensitivity to deep UV light. Scanning exposure time necessary for a 4-in wafer is about 25 s. The MRS exhibits dry etching resistance superior to that of an AZ-type positive resist. Furthermore, MRS is not adversely affected by reflected light from stepped aluminum surfaces. Application of MRS should open the way to realization of a practical deep UV 1:1 projection lithography featuring high resolution and throughput.     

A 2-µm silicon-gate C-MOS/SOS technology

A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters as a function of channel length is presented. Circuit performance was characterized using a ring oscillator and a pattern generator. The ring oscillator exhibited stage delay as small as 220 ps at 5 V and an associated speed power product of less than 5 pJ. The pattern generator achieved an 80-MHz data rate. The potential of this technology for extension to submicrometer geometries was demonstrated by fabrication of discrete transistors with O.5-µm channel lengths.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Optimization of the composition of a new MRS-type negative resist

Sensitizer concentration is optimized for a new negative photoresist, MRL (Micro Resist for Longer wavelengths) with the assistance of computer simulation. The resist, which has photosensitivity in the ordinary UV region, resembles a deep UV resist MRS in terms of light absorption characteristic. It is found that a photosensitizer concentration of 20 wt% (based on the resin) is suitable for a reduction projection exposure system that utilizes UV light at 365 nm. A steep profile resist image of 0.7-µm lines and 0.7-µm spaces in a 1.0-µm thick resist layer is obtained using the MRL of optimized composition and the exposure system.     

A new grating-type gold-n-type silicon Schottky-barrier photodiode

The new grating-type Au-n-type Si Schottky-barrier photodiode has been fabricated and analyzed. The device is constructed with a new structure of contact mask. The mask forms a grating of gold film over the contacting silicon substrate. The grating spacing is so chosen that even at zero bias the interfacial layer between the silicon substrate and the gold gratings is completely depleted. The device is fabricated on an n-type silicon wafer of ∼1300-Ω.cm resistivity, and the grating spacing is 12.5 µm. An analysis is performed to determine the I-V characteristics, the spectral dependence of the quantum yield, the responsivity, and the noise characteristics of the photodiode. It is found that without optimization the device has a bandwidth of ∼1 GHz and responsivity of 0.63 A/W at λ =0.9 µm.     

Intensity spatial filtering applied to defect detection in integrated circuit photomasks

An intensity spatial filter has been devised and used for the semiautomatic photoelectric detection of 2.5-µ defects in 5-cm²photolithography masks for silicon integrated circuits. The filter is based on a simple geometric approximation to the form factor or envelope function for the intensity in the Fourier-transform plane, and permits small-area diffraction-limited illumination. This approach complements the Watkins' method.     

Effects of alumina substrate surface defects on thin-film interconnect patterns

An investigation was made into the occurrence of substrate surface defects, such as surface pits, low-density regions and burrs, and their effect on fine-line thin-film conductor patterns fabricated on the substrate. Substrate surface quality was characterized through examination of fine-line thin-film test patterns (50-µm lines on 100-µm centers). The results of these observations are summarized in terms of N^-, the substrate surface defect density, and f, the frequency of resultant conductor-line imperfections greater in width than some critical size δ. The parameter f is directly related to the expected yield Y for a thin-film interconnect circuit with fine-line conductor length L. A quantitative model is developed which accurately relates N and f to N^-(x), the size distribution of surface voids; δ, the critical extent of defect overlap on a conductor line; and D, the width of the conductor line. Application of the model to prediction of the dependence of f and Y on various parameters led to the conclusion that it is important to establish objective criteria as to what constitutes a conductor-line imperfection. A change in definition from the extent to which a conductor line appeared to be open to the overlap of a substrate defect on a conductor line resulted in a tenfold increase in f. This change would result in a fourfold decrease in Y for the case of an interconnect pattern with 500 cm of 50-µm lines. A change in δ from D/3 to 2D/3 resulted in a sixfold decrease in f and a corresponding increase in yield from 20 to 80 percent for the same interconnect circuit.     

Boron ion implantation in silicon through selectively deposited tungsten films

The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p⁺-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-Vcharacteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2-SiO2interface are the contributing generation-recombination sites.     

A simple mask aligner and printing frame for conformable photomask lithography

Conformable photomask lithography allows submicrometer lines to be replicated by contact printing. Surface acoustic wave devices with 0.4-µm lines have been produced using this technique. A mask aligner and printing frame have been designed which feature micrometer controlledXandYmotion, rotation about the center of the viewing field, and both top and bottom illumination of mask and substrate. The construction and use of the apparatus, which is based on a toolmaker's microscope, is fully described.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

Fabrication of a low-noise beam-leaded microwave bipolar transistor by electron- and photolithography

A low-noise beam-leaded microwave bipolar transistor was fabricated with a combination of electron- and photolithography. Four of the eleven levels which were related to the patterning of the active region were patterned directly on the silicon wafers by the Bell Laboratories Electron Beam Exposure System (EBES). The registration tolerance of the 1-µm emitter stripes to the thin-gold metallization fingers was ± ¼-µm. This was routinely achieved on the 2-in wafers for all the levels written on EBES. The device processing employed a modified self-aligned emitter process which allows very highly doped inactive base and emitters without the problem of soft emitter-base junction. RF measurements of typical transistors show a minimum noise figure of 1.8 dB and an available gain of 12 dB at 1.7 GHz.