LEAP: An Accurate Defect-Free IDDQ Estimator

The quiescent current (I _DDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I _DDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I _DDQ test. In this work, we present a method to estimate accurately the non-defective I _DDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free I _DDQ currents.     

I DDQ testing: A review

Quiescent power supply current (I _DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I _DDQ testing. Next, the use of I _DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.     

SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

I _DDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theI _DDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousI _DDQ testing, better defect diagnosis, and can be used for deep sub-micronI _DDQ testing.     

Quietest: A methodology for selecting I DDQ test vectors

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I _DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I _DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I _DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I _DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.     

Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study

In this paper we present an experimental study on the effectivenessof incorporating at-speed I _DDQ testing with traditionalBIST for improved test coverage. The high speed I _DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 differentrealistic CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI _DDQ testing for these realistic faults. An interestingfinding of our study is that I _DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.     

I DDQ testing in CMOS digital ASICs

I _DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I _DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I _DDQ measurement distribution, effects of multiple I _DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I _DDQ testing was implemented are reviewed. The methods used to establish I _DDQ test limits and implement the I _DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.     

Replacing I DDQ Testing: With Variance Reduction

This work is part of our effort to find an alternative to I _DDQ testing. Specifically, this paper presents our variance reduction post-processing approach in order to replace I _DDQ. It describes our test procedure based on Delta I _DDQ histograms. It shows how this test procedure can help to reduce variance, optimize test resources and reduce the impact of process drifting and resolution loss caused by the expected I _DDQ growth. Another practical aspect is discussed, namely the use of the proposed test procedure in a production test. We propose a new distribution model and revisit some experimental data, which provides a better understanding of the relationship between defect and fault. The results obtained so far confirm the pertinence of our test approach and the necessity of keeping current testing alive.     

Reducing the CMOS RAM test complexity withI DDQ and voltage testing

In this article, we outline a RAM test methodology taking into accountI _DDQ and voltage based March tests. RAM test cost forms a significantly large portion of its total production cost and is projected to increase even further for future RAM generations.I _DDQ testing can be utilized to reduce this cost. However, owing to architectural and operational constrains of RAMs, a straight forward application ofI _DDQ testing has very limited defect detection capability. These constrains are removed by creating anI _DDQ test mode in RAMs. All bridging defects in RAM matrix, including the gate oxide defects, are detected by fourI _DDQ measurements. TheI _DDQ test is then supplemented with voltage based March test to detect the defects (opens, data retention) that are not detectable usingI _DDQ technique. The combined test methodology reduces the algorithmic test complexity for a given SRAM fault model from 16n to 5n+4I _DDQ measurements.     

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing

The effectiveness of single threshold I _DDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta I _DDQ is identified as one alternative for deep submicron current measurements. Often delta I _DDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the I _DDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate I _DDQ limits for normal and stressed operating conditions of 0.18 m n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed I _DDQ testing is also investigated.     

Algorithms for I DDQ measurement based diagnosis of bridging faults

In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I _DDQ measurement based testing.Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm.In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I _DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I _DDQ measurements.A preliminary version of this work was presented at the 29th ACM/IEEE Design Automation Conference, 1992.Research Partially Supported by NSF Grant No. MIP-9102509.This work was performed when the author was with the Dept. of Computer Science, State University of New York at Buffalo.     

Algorithms to select I DDQ measurement points to detect bridging faults

I _DDQ measurement is a time consuming process. Thus, reducing the number of I _DDQ measurements have a great impact on the test time. Carefully selecting a few I _DDQ measurement points is therefore an important problem. This problem has been studied for detecting leakage faults but not for bridging faults. We present novel algorithms to select I _DDQ measurement points to detect bridging faults. Experimental results obtained are very encouraging. The method can also be used: by test generators to compress I _DDQ test sets; and to maximize the fault coverage when a fixed number of measurement points are given.Research supported by NSF Grant No. MIP-9102509.     

Diagnosis of leakage faults with I DDQ

Recently there has been renewed interest in fault detection in static CMOS circuits through I _DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.     

Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ

Abnormal I _DDQ (Quiescent V _DD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to enhance the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal I _DDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal I _DDQ exists in normal logic state or not.     

Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments

The goal of this work is to analyze the performance of PN junction-based Built-in Current Sensors (BICS) for I _DDQ testing. Two types of BIC Sensors are analyzed: one based on a simple PN junction as the sensing element (DBICS), and the other based on a lateral BJT (PBICS). The sensitivity, speed and performance of the BICS are studied by showing their dependence on circuit parameters. Design constraints of such sensors in order to achieve performance criteria on CUT and BICS are analyzed. The dynamic analysis of the BICS is compared with experimental results when the PN junction BICS are used on a CMOS circuit.     

Design and Realization of a Built-In Current Sensor for IDDQ Testing and Power Dissipation Measurement

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage of quiescent current (I_DDQ) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I_DDQ testing. This paper presents a new BICS suitable for power dissipation measurement and I_DDQ testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 m technology. Practical results demonstrate that a very good measurement accuracy can be achieved.     

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses I _DDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of I _DDQ contour plots. A family of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.     

IDDQ Testing of Submicron CMOS—by Cooling?

The usability of I _DDQ testing is limited by the subthreshold currents of the low-V _T, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of –75...25 Centigrade. The subthreshold currents decrease by a factor of about 100–1000 by cooling-down the chip to –75 Centigrade.