一种齐纳二极管控制式轨对轨CMOS运算放大器

采用0.6μm CMOS工艺,设计了一种齐纳二极管控制式轨对轨运算放大器.该运放采用了3.3V单电源供电,其输入共模范围和输出信号摆幅接近于地和电源电压,即所谓输入和输出电压范围轨对轨.该运放的小信号增益为82dB,单位增益带宽为12.34MHz,相位裕度为68°.由于电路简单,工作稳定,输入输出线性动态范围宽,非常适合于SOC芯片内集成.文中主要讨论该轨对轨运算放大器的原理,性能及设计方法,并进行了模拟仿真.     

一种轨对轨CMOS运算放大器的设计

基于0.6μmCMOS工艺,设计了一种轨对轨运算放大器。该运算放大器采用了3.3V单电源供电,其输入共模范围和输出信号摆幅接近于地和电源电压,即所谓输入和输出电压范围轨对轨。该运放的小信号增益为77dB,单位增益带宽为4.32MHz,相位裕度为79°。由于电路简单,工作稳定,输入输出线性动态范围宽,非常适合于SOC芯片内集成。     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

一种低失调CMOS轨到轨运算放大器研究

基于CMOS工艺设计了一款轨到轨运算放大器,整体电路包括偏置电路、输入级、输出级以及ESD保护电路。电路中的输入级使用了一种全新的架构,通过一对耗尽型NMOS管作为输入管,实现轨到轨输入,同时在输入级采用了共源共栅结构,能够提供较高的共模输入范围和增益;在输出级,为了得到满摆幅输出而采用了AB类输出级;同时ESD保护电路采用传统的GGMOS电路,耐压大于2 kV。经过仿真后可知,电路的输入偏置电流为150 fA,在负载为100 kΩ的情况下,输出最高和最低电压可达距电源轨和地轨的20 mV范围内,当电源电压为5 V时能获得80 dB的CMRR和120 dB的增益,相位裕度约为50°,单位增益带宽约为1.5 MHz。     

一种恒跨导高增益轨到轨运算放大器

基于TSMC 0.18 μm CMOS工艺,设计了一种新颖的恒跨导高增益轨到轨运算放大器。输入级仅由NMOS管差分对构成,采用电平移位及两路复用选择器控制技术,在轨到轨共模输入范围内实现了输入级恒跨导。中间级采用折叠式共源共栅放大器结构,运算放大器能获得高增益。输出级采用前馈型AB类推挽放大器,实现轨到轨全摆幅输出。利用密勒补偿技术进行频率补偿,运算放大器工作稳定。仿真结果表明,在1.8 V电源电压下,该运算放大器的直流开环增益为129.3 dB,单位增益带宽为7.22 MHz,相位裕度为60.1°,整个轨到轨共模输入范围内跨导的变化率为1.44%。     

基于单一PMOS差分对的轨到轨输入运算放大器设计

基于国内某CMOS工艺设计了一种单一PMOS差分对的轨到轨输入、恒跨导CMOS运算放大器。输入级电路采用折叠共源共栅结构,通过体效应动态调节输入管的阈值电压扩展共模输入范围到正负电源轨,恒定共模输入范围内的跨导,自级联电流镜有源负载将差分输入转换为单端输出;输出级电路采用AB类结构实现轨到轨输出,线性跨导环确定输出管的静态偏置电流。在5 V电源电压,2.5 V共模电压,1 MΩ负载条件下,经Spectre仿真验证,该运算放大器开环增益为119 dB,相位裕度为58°,共模输入范围为0.0027～4.995 V,共模范围内跨导变化小于3%,实现了轨到轨输入共模范围内的跨导恒定。     

恒跨导轨对轨CMOS运算放大器的设计

为了提高运算放大器对电源电压的利用率,基于GSMC 0.18 μm CMOS工艺模型,设计了一种高增益恒跨导轨对轨CMOS运算放大器。该运算放大器的输入级采用了互补差分对,并通过3倍电流镜法保证输入级总跨导在整个共模输入范围内恒定;为了获得较大的增益和输出摆幅,中间级采用了折叠式共源共栅结构;输出级采用了AB类输出控制电路,使输出摆幅基本实现了轨对轨。在3.3 V供电电压以及1.6 V输入电压下,该放大器的直流增益为126 dB,单位增益带宽为50 MHz,相位裕度为65°。电路结构简单,易于调试,可大大缩减设计周期和成本。     

轨到轨电压比较器的设计

比较器在模数转换及其他模拟功能模块中都是非常重要的器件,其速度和精度直接影响模块的功能.采用SMIC 0.18 CMOS混合信号工艺,设计了一种轨到轨电压比较器,电路结构主要包括前置放大器、锁存器和输出缓冲电路,此外,采用一种β倍增的自偏置基准电路提供偏置电流.结果表明,在3.3V的供电电压下,提供共模范围为300 mV～3.3 V的信号,可分辨输入信号的最小频率为200 MHz,单级运放相位裕度大于60°,输出信号占空比为40％～60％,比较阈值约为10 mV,输入输出延时小于5 ns,功耗小于18 mW,版图面积小于200 μm× 150 μm.该比较器的失真较小,在整个输入信号范围内有较高的共模抑制比,较大限度地提高了电路的性能.     

一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器

设计了一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器.输入级采用PMOS差分对结构,通过电荷泵产生高于电源电压的输入级内电源,使运放在轨到轨输入范围能正常工作并保持输入跨导恒定.电荷泵电路所需的时钟信号通过内部振荡器电路产生,再通过电压自举电路和时序电路产生所需电平的非交叠开关控制信号,最后利用时间交织结构输出连续稳定的高压内电源.在电荷泵实现中还采用了辅助开关结合跟随运放的结构降低了主开关在切换时的毛刺.该运放在折叠式共源共栅结构中使用增益自举结构提高了总体增益,输出级采用class AB类输出结构实现轨到轨输出.该运算放大器基于0.5μm CMOS工艺完成电路与版图设计,仿真结果表明,在5 V电源电压下,直流增益为150.76 dB,单位增益带宽为53.407 MHz,相位裕度为96.1°,输入级跨导在轨到轨输入共模范围内的变化率为0.001 25%.     

基于单差分对输入级的新型轨到轨运算放大器设计

本文基于CMOS工艺设计了一种新型的轨到轨集成运算放大器。对比分析传统轨到轨输入级设计的优劣,该运放选择采用单差分对输入级结构,使用耗尽型NMOS管作为输入对管,利用耗尽型NMOS管的体效应以及对输入级电路结构的优化,实现轨到轨输入,以AB类输出级结构实现轨到轨输出。经过Cadence仿真验证,工作在5 V单电源供电下,共模输入电压范围可以实现满轨0～5 V,增益高达141.1 dB,带宽1.7 MHz,相位裕度55.4°,具有较低的输入失调电压264μV、输入偏置电流9 pA。整体电路实现了近乎满轨的轨到轨的输出电压摆幅,达到轨到轨运算放大器的设计要求。     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

一种恒跨导CMOS运算放大器的设计

设计了一种宽带轨对轨运算放大器,此运算放大器在3.3 V单电源下供电,采用电流镜和尾电流开关控制来实现输入级总跨导的恒定。为了能够处理宽的电平范围和得到足够的放大倍数,采用用折叠式共源共栅结构作为前级放大。输出级采用AB类控制的轨对轨输出。频率补偿采用了级联密勒补偿的方法。基于TSMC 2.5μm CMOS工艺,电路采用HSpice仿真,该运放可达到轨对轨的输入/输出电压范围。     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

采用输入信号适配技术的BiCMOS运放

为了满足高性能开关电源中集成运放的应用需要,设计了一种结构简单且具有轨对轨输出的运算放大器.该运放基于0.5μm BiCMOS 工艺,采用浮动输出的输入信号适配器(ISAFO),将输入信号放大至差分输入级的工作区域,从而实现了轨对轨的运行.对所设计的运放进行了仿真分析,结果表明在工作电源电压为±0.75 V、外接100 kΩ电阻的条件下,该运放的直流开环增益达到了102 dB,单位增益-带宽为6.35 MHz,相位裕度为62.5°,而功耗仅约为150 μW.所设计的运放具有很宽的共模输入范围及较高的增益,所以特别适用于开关电源的误差放大器、过流、过压和过热保护模块中.     

A rail-to-rail, constant gain, buffered op-amp for real time videoapplications

Inspired by Hogervorst et al's current switch idea, a buffered output stage operational amplifier was designed, which has high frequency, high dc gain, and rail-to-rail constant transconductance (G _m). This operational amplifier is the output stage of an analog/digital system which implements a Gabor convolution for real-time dynamic image processing and it is designed to interface the external analog-to-digital converter (ADC) with a very heavy load. The op amp was fabricated by the MOSIS service in a 2-μm, n-well CMOS, double polysilicon, double metal technology. The fabricated circuit operates from a single 5 V power supply and dissipates 10 mW. The open loop-gain of the fabricated circuit, A_vol, was measured as 67.2 dB for a 163 Ω∥33 pF load. Other dc and ac characteristics were measured for a 50 Ω∥33 pF load. The unify gain-bandwidth (GBW) was measured to be 11.4 MHz, the rising slew rate (SR+) 20.4 V/μs, the falling slew rate (SR-) 18.8 V/μs, and the offset voltage (V_off) 1 mV. The output swings with an amplitude of 3.24 V between 0.88 V and 4.12 V, which matches the input signal specifications of the ADC. In addition to rail-to-rail output voltage swing, the opamp has a constant G_m over the whole common mode (CM) voltage range     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。     

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion. The improved Miller OTA has been successfully verified in a standard 0.35-mum CMOS process. Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.